[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Configure PCIe for APL/GLK WiFi
Venkateswarlu V Vinjamuri (Code Review)
gerrit at coreboot.org
Mon Apr 9 20:57:40 CEST 2018
Venkateswarlu V Vinjamuri has uploaded this change for review. ( https://review.coreboot.org/25570
Change subject: soc/intel/apollolake: Configure PCIe for APL/GLK WiFi
......................................................................
soc/intel/apollolake: Configure PCIe for APL/GLK WiFi
Creates a common asl include file for PCIe power state methods.
This allows ports to be enabled independently.
Configures PCIe device ID's for APL/GLK. APL uses root port 1
(PCIe ID 14.0) and GLK Octopus uses root port 3 (PCIe 13.0)
for discrete PCIe wifi card.
BUG=None
BRANCH=None
TEST=use Stone Peak discrete wifi card and test s0ix.
Change-Id: Idd1e6d502f3e7ecc2050a6c19bfe7bf99b163985
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
M src/soc/intel/apollolake/acpi/pcie.asl
A src/soc/intel/apollolake/acpi/pcie_port.asl
M src/soc/intel/apollolake/chip.c
3 files changed, 136 insertions(+), 105 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/25570/1
diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl
index 050f2f0..03c0c63 100644
--- a/src/soc/intel/apollolake/acpi/pcie.asl
+++ b/src/soc/intel/apollolake/acpi/pcie.asl
@@ -13,114 +13,20 @@
* GNU General Public License for more details.
*/
+/* PCIe Ports */
+
Device (RP01)
{
+ Name (_ADR, 0x00130000)
+ Name (_DDN, "PCIe-A 0")
+
+ #include "pcie_port.asl"
+}
+
+Device (RP02)
+{
Name (_ADR, 0x00140000)
Name (_DDN, "PCIe-B 0")
- Name (PDST, 0) /* present Detect status */
- /* lowest D-state supported by
- * PCIe root port during S0 state
- */
- Name (_S0W, 4)
-
- /* Dynamic Opregion needed to access registers
- * when the controller is in D3 cold
- */
- OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
- Field (PX01, AnyAcc, NoLock, Preserve)
- {
- Offset(0x5A),
- , 6,
- PDS, 1, /* 6, Presence detect Change */
- Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */
- , 2,
- L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
- L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
- Offset(0xF4), /* BLKPLLEN */
- , 10,
- BPLL, 1,
- }
-
- OperationRegion (PX02, PCI_Config, 0x338, 0x4)
- Field (PX02, AnyAcc, NoLock, Preserve)
- {
- , 26,
- BDQA, 1 /* BLKDQDA */
- }
-
- PowerResource (PXP, 0, 0)
- {
- /* Define the PowerResource for PCIe slot */
- Method (_STA, 0, Serialized)
- {
- Store (PDS, PDST)
- If (LEqual (PDS, 1)) {
- Return (0xf)
- } Else {
- Return (0)
- }
- }
-
- Method (_ON, 0, Serialized)
- {
- If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
- /* Enter this condition if device
- * is connected
- */
-
- /* De-assert PERST */
- \_SB.PCI0.PRDA (\PRT0)
-
- Store (0, BDQA) /* Set BLKDQDA to 0 */
- Store (0, BPLL) /* Set BLKPLLEN to 0 */
-
- /* Set L23_Rdy to Detect Transition
- * (L23R2DT)
- */
- Store (1, L23R)
- Sleep (16)
- Store (0, Local0)
-
- /* Delay for transition Detect
- * and link to train
- */
- While (L23R) {
- If (Lgreater (Local0, 4)) {
- Break
- }
- Sleep (16)
- Increment (Local0)
- }
- } /* End PDS condition check */
- }
-
- Method (_OFF, 0, Serialized)
- {
- /* Set L23_Rdy Entry Request (L23ER) */
- If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
- /* enter this condition if device
- * is connected
- */
- Store (1, L23E)
- Sleep (16)
- Store (0, Local0)
- While (L23E) {
- If (Lgreater (Local0, 4)) {
- Break
- }
- Sleep (16)
- Increment (Local0)
- }
- Store (1, BDQA) /* Set BLKDQDA to 1 */
- Store (1, BPLL) /* Set BLKPLLEN to 1 */
-
- /* Assert PERST */
- \_SB.PCI0.PRAS (\PRT0)
- } /* End PDS condition check */
- } /* End of Method_OFF */
- } /* End PXP */
-
- Name(_PR0, Package() { PXP })
- Name(_PR3, Package() { PXP })
+ #include "pcie_port.asl"
}
diff --git a/src/soc/intel/apollolake/acpi/pcie_port.asl b/src/soc/intel/apollolake/acpi/pcie_port.asl
new file mode 100644
index 0000000..ea8bfe3
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pcie_port.asl
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Include in each PCIe Root Port device */
+
+/* lowest D-state supported by
+ * PCIe root port during S0 state
+ */
+Name (_S0W, 4)
+
+Name (PDST, 0) /* present Detect status */
+
+/* Dynamic Opregion needed to access registers
+ * when the controller is in D3 cold
+ */
+OperationRegion (PX01, PCI_Config, 0x00, 0xFF)
+Field (PX01, AnyAcc, NoLock, Preserve)
+{
+ Offset(0x5A),
+ , 6,
+ PDS, 1, /* 6, Presence detect Change */
+ Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */
+ , 2,
+ L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */
+ L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */
+ Offset(0xF4), /* BLKPLLEN */
+ , 10,
+ BPLL, 1,
+}
+
+OperationRegion (PX02, PCI_Config, 0x338, 0x4)
+Field (PX02, AnyAcc, NoLock, Preserve)
+{
+ , 26,
+ BDQA, 1 /* BLKDQDA */
+}
+
+PowerResource (PXP, 0, 0)
+{
+ /* Define the PowerResource for PCIe slot */
+ Method (_STA, 0, Serialized)
+ {
+ Store (PDS, PDST)
+ If (LEqual (PDS, 1)) {
+ Return (0xf)
+ } Else {
+ Return (0)
+ }
+ }
+
+ Method (_ON, 0, Serialized)
+ {
+ If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
+ /* Enter this condition if device
+ * is connected
+ */
+
+ /* De-assert PERST */
+ \_SB.PCI0.PRDA (\PRT0)
+
+ Store (0, BDQA) /* Set BLKDQDA to 0 */
+ Store (0, BPLL) /* Set BLKPLLEN to 0 */
+
+ /* Set L23_Rdy to Detect Transition
+ * (L23R2DT)
+ */
+ Store (1, L23R)
+ Sleep (16)
+ Store (0, Local0)
+
+ /* Delay for transition Detect
+ * and link to train
+ */
+ While (L23R) {
+ If (Lgreater (Local0, 4)) {
+ Break
+ }
+ Sleep (16)
+ Increment (Local0)
+ }
+ } /* End PDS condition check */
+ }
+
+ Method (_OFF, 0, Serialized)
+ {
+ /* Set L23_Rdy Entry Request (L23ER) */
+ If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) {
+ /* enter this condition if device
+ * is connected
+ */
+ Store (1, L23E)
+ Sleep (16)
+ Store (0, Local0)
+ While (L23E) {
+ If (Lgreater (Local0, 4)) {
+ Break
+ }
+ Sleep (16)
+ Increment (Local0)
+ }
+ Store (1, BDQA) /* Set BLKDQDA to 1 */
+ Store (1, BPLL) /* Set BLKPLLEN to 1 */
+
+ /* Assert PERST */
+ \_SB.PCI0.PRAS (\PRT0)
+ } /* End PDS condition check */
+ } /* End of Method_OFF */
+} /* End PXP */
+
+Name(_PR0, Package() { PXP })
+Name(_PR3, Package() { PXP })
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1dd6daf..9f2cebb 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -113,6 +113,8 @@
/* PCIe */
case PCH_DEVFN_PCIE1:
return "RP01";
+ case PCH_DEVFN_PCIE5:
+ return "RP02";
}
return NULL;
--
To view, visit https://review.coreboot.org/25570
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idd1e6d502f3e7ecc2050a6c19bfe7bf99b163985
Gerrit-Change-Number: 25570
Gerrit-PatchSet: 1
Gerrit-Owner: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180409/e1bdb826/attachment-0001.html>
More information about the coreboot-gerrit
mailing list