[coreboot-gerrit] Change in coreboot[master]: src/cpu/intel: Add model_f6x
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Mon Apr 9 15:11:55 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/25565
Change subject: src/cpu/intel: Add model_f6x
......................................................................
src/cpu/intel: Add model_f6x
Change-Id: I6003ec0f4d4245ce5fc9c1f38e555bfcfa1c22b5
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/intel/Kconfig
M src/cpu/intel/microcode/microcode.c
A src/cpu/intel/model_f6x/Kconfig
A src/cpu/intel/model_f6x/Makefile.inc
A src/cpu/intel/model_f6x/model_f6x_init.c
M src/cpu/intel/socket_LGA775/Kconfig
M src/cpu/intel/socket_LGA775/Makefile.inc
7 files changed, 76 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/25565/1
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 612b62e..7ca574b 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -19,6 +19,7 @@
source src/cpu/intel/model_f2x/Kconfig
source src/cpu/intel/model_f3x/Kconfig
source src/cpu/intel/model_f4x/Kconfig
+source src/cpu/intel/model_f6x/Kconfig
source src/cpu/intel/ep80579/Kconfig
source src/cpu/intel/haswell/Kconfig
# Sockets/Slots
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 59c3b8a..d8c7e72 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -165,6 +165,7 @@
while (microcode_len >= sizeof(*ucode_updates)) {
/* Newer microcode updates include a size field, whereas older
* containers set it at 0 and are exactly 2048 bytes long */
+ printk(BIOS_SPEW, "found microcode for sig=0x%x\n", ucode_updates->sig);
if (ucode_updates->total_size) {
update_size = ucode_updates->total_size;
} else {
diff --git a/src/cpu/intel/model_f6x/Kconfig b/src/cpu/intel/model_f6x/Kconfig
new file mode 100644
index 0000000..ede6a4a
--- /dev/null
+++ b/src/cpu/intel/model_f6x/Kconfig
@@ -0,0 +1,8 @@
+config CPU_INTEL_MODEL_F6X
+ bool
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f6x/Makefile.inc b/src/cpu/intel/model_f6x/Makefile.inc
new file mode 100644
index 0000000..0e3ec50
--- /dev/null
+++ b/src/cpu/intel/model_f6x/Makefile.inc
@@ -0,0 +1,3 @@
+ramstage-y += model_f6x_init.c
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f6x/microcode.bin
diff --git a/src/cpu/intel/model_f6x/model_f6x_init.c b/src/cpu/intel/model_f6x/model_f6x_init.c
new file mode 100644
index 0000000..496f563
--- /dev/null
+++ b/src/cpu/intel/model_f6x/model_f6x_init.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+
+static void model_f6x_init(struct device *cpu)
+{
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+
+ if (!intel_ht_sibling()) {
+ /* MTRRs are shared between threads */
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+
+ /* Update the microcode */
+ intel_update_microcode_from_cbfs();
+ }
+
+ /* Enable the local CPU APICs */
+ setup_lapic();
+
+ /* Start up my CPU siblings */
+ intel_sibling_init(cpu);
+};
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_f6x_init,
+};
+
+static const struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x0f62 },
+ { X86_VENDOR_INTEL, 0x0f64 },
+ { X86_VENDOR_INTEL, 0x0f65 },
+ { X86_VENDOR_INTEL, 0x0f68 },
+ { 0, 0 },
+};
+
+static const struct cpu_driver model_f6x __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8b227bd..0d0cd00 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -8,7 +8,7 @@
select CPU_INTEL_MODEL_6FX
select CPU_INTEL_MODEL_F3X
select CPU_INTEL_MODEL_F4X
-# select CPU_INTEL_MODEL_F6X
+ select CPU_INTEL_MODEL_F6X
# select CPU_INTEL_MODEL_1066X
select CPU_INTEL_MODEL_1067X
select MMX
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index ffcd1cb..8eef023 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -1,7 +1,7 @@
subdirs-y += ../model_6fx
subdirs-y += ../model_f3x
subdirs-y += ../model_f4x
-#subdirs-y += ../model_f6x
+subdirs-y += ../model_f6x
#subdirs-y += ../model_1066x
subdirs-y += ../model_1067x
subdirs-y += ../../x86/tsc
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6003ec0f4d4245ce5fc9c1f38e555bfcfa1c22b5
Gerrit-Change-Number: 25565
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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