[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Configure all possible GFX DSM memory reserve range

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/25562


Change subject: soc/intel/common: Configure all possible GFX DSM memory reserve range
......................................................................

soc/intel/common: Configure all possible GFX DSM memory reserve range

Intel internal graphics preallocated memory size should be selected from
below lists as per Intel FSP UPD header:

0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB,
0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB,
0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB,
0xFC:52MB, 0xFD:56MB, 0xFE:60MB

This patch ensures that coreboot can report the same preallocated
memory range for intel grapics during memory layout calculation.

TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB
and coreboot could able to calculate GFX DSM range accordingly.

Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/common/block/systemagent/systemagent_early.c
1 file changed, 21 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/25562/1

diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index 4abc15f..a24b3b6 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -144,11 +144,31 @@
 	return pci_read_config16(SA_DEV_ROOT, GGC);
 }
 
+/*
+ * Internal Graphics Pre-allocated Memory - As per Intel FSP UPD Header
+ * definition, size of memory preallocatred for internal graphics can be
+ * configured based on below lists:
+ *
+ * 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB,
+ * 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB,
+ * 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB,
+ * 0xFE:60MB
+ */
 size_t sa_get_dsm_size(void)
 {
-	return (((sa_get_ggc_reg() & G_GMS_MASK) >> G_GMS_OFFSET) * 32*MiB);
+	uint32_t prealloc_memory;
+	uint16_t ggc;
+
+	ggc = sa_get_ggc_reg();
+	prealloc_memory = ((ggc & G_GMS_MASK) >> G_GMS_OFFSET);
+
+	if (prealloc_memory < 0xF0)
+		return (prealloc_memory * 32*MiB);
+	else
+		return ((prealloc_memory - 0xEF) * 4*MiB);
 }
 
+
 static uintptr_t sa_get_gsm_base(void)
 {
 	/* All regions concerned for have 1 MiB alignment. */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58
Gerrit-Change-Number: 25562
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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