[coreboot-gerrit] Change in coreboot[master]: [WIP]soc/intel/cannonlake: Enable early mmc CMD0, CMD1
Bora Guvendik (Code Review)
gerrit at coreboot.org
Wed Apr 4 02:19:52 CEST 2018
Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/25515
Change subject: [WIP]soc/intel/cannonlake: Enable early mmc CMD0, CMD1
......................................................................
[WIP]soc/intel/cannonlake: Enable early mmc CMD0, CMD1
In order to improve boot time via emmc, enable Intel common
code that sends CMD0 and CMD1 early in firmware.
Change-Id: I854cf5d323062fde1c07dd0816af127efebaa195
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/cannonlake/early_mmc.c
M src/soc/intel/cannonlake/include/soc/iomap.h
M src/soc/intel/cannonlake/romstage/romstage.c
5 files changed, 69 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/25515/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index fc73210..50c86ff 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -42,6 +42,7 @@
select SOC_AHCI_PORT_IMPLEMENTED_INVERT
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_EARLY_MMC_WAKE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_CPU
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 47f06aa..383705c 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -31,6 +31,7 @@
romstage-y += reset.c
romstage-y += spi.c
romstage-$(CONFIG_UART_DEBUG) += uart.c
+romstage-y += early_mmc.c
ramstage-y += acpi.c
ramstage-y += chip.c
diff --git a/src/soc/intel/cannonlake/early_mmc.c b/src/soc/intel/cannonlake/early_mmc.c
new file mode 100644
index 0000000..1112210
--- /dev/null
+++ b/src/soc/intel/cannonlake/early_mmc.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/early_mmc.h>
+#include <intelblocks/gpio.h>
+
+
+static const struct pad_config mmc_early_gpios[] = {
+ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* EMMC_CMD */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DAT0 */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DAT1 */
+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), /* EMMC_DAT2 */
+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* EMMC_DAT3 */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* EMMC_DAT4 */
+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* EMMC_DAT5 */
+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* EMMC_DAT6 */
+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* EMMC_DAT7 */
+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */
+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* EMMC_RST_ODL */
+};
+
+int soc_set_mmc_gpios(void)
+{
+ gpio_configure_pads(&mmc_early_gpios[0], ARRAY_SIZE(mmc_early_gpios));
+
+ return 0;
+}
+
+void soc_get_mmc_frequencies(uint32_t* f_min, uint32_t* f_max)
+{
+ *f_min = 400000;
+ *f_max = 25000000;
+}
+
+int soc_set_mmc_dll(struct mmc_dll_params* params)
+{
+ params->emmc_tx_data_cntl1 = 0x0B0B;
+ params->emmc_tx_data_cntl2 = 0x1C292929;
+ params->emmc_rx_cmd_data_cntl1 = 0x1C101616;
+ params->emmc_rx_cmd_data_cntl2 = 0x21806;
+ params->emmc_rx_strobe_cntl = 0x1616;
+ params->emmc_tx_cmd_cntl = 0x505;
+
+ return 0;
+}
diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h
index 2a3608c..c2044a0 100644
--- a/src/soc/intel/cannonlake/include/soc/iomap.h
+++ b/src/soc/intel/cannonlake/include/soc/iomap.h
@@ -86,4 +86,6 @@
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
#define P2SB_SIZE (16 * MiB)
+#define PRERAM_MMC_BASE_ADDRESS 0xFE400000
+
#endif
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 759c2c9..3784b66 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -22,6 +22,7 @@
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/cse.h>
+#include <intelblocks/early_mmc.h>
#include <intelblocks/pmclib.h>
#include <memory_info.h>
#include <soc/intel/common/smbios.h>
@@ -128,6 +129,11 @@
if (postcar_frame_init(&pcf, 1 * KiB))
die("Unable to initialize postcar frame.\n");
+ if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE)) {
+ if (early_mmc_wake_hw() < 0)
+ printk(BIOS_DEBUG, "Early mmc initilization failed \n");
+ }
+
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I854cf5d323062fde1c07dd0816af127efebaa195
Gerrit-Change-Number: 25515
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
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