[coreboot-gerrit] Change in coreboot[master]: [do not merge] add i945G based mainboard
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue Apr 3 17:46:21 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/25509
Change subject: [do not merge] add i945G based mainboard
......................................................................
[do not merge] add i945G based mainboard
82945GC - 82801Gx - W83627EHG
CPU: family 0f, model 06, stepping 05: microcode loaded correctly.
it didn't boot correctly.
The system halt on "XZ-compressed data corrupt".
Here is a screeshot:
https://www.dropbox.com/s/fa3jlsltiq6st0z/XZ-compressed_data_is_corrupt.jpg?dl=0
and here is a log: https://pastebin.com/aMrN5jwj
Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/intel/Kconfig
M src/cpu/intel/microcode/microcode.c
A src/cpu/intel/model_f6x/Kconfig
A src/cpu/intel/model_f6x/Makefile.inc
A src/cpu/intel/model_f6x/model_f6x_init.c
M src/cpu/intel/socket_LGA775/Kconfig
M src/cpu/intel/socket_LGA775/Makefile.inc
M src/cpu/intel/speedstep/acpi.c
M src/cpu/intel/speedstep/speedstep.c
M src/device/dram/ddr2.c
A src/mainboard/nec/945g-m4/Kconfig
A src/mainboard/nec/945g-m4/Kconfig.name
A src/mainboard/nec/945g-m4/Makefile.inc
A src/mainboard/nec/945g-m4/acpi/ec.asl
A src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl
A src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
A src/mainboard/nec/945g-m4/acpi/mainboard.asl
A src/mainboard/nec/945g-m4/acpi/platform.asl
A src/mainboard/nec/945g-m4/acpi/superio.asl
A src/mainboard/nec/945g-m4/acpi/thermal.asl
A src/mainboard/nec/945g-m4/acpi/video.asl
A src/mainboard/nec/945g-m4/acpi_tables.c
A src/mainboard/nec/945g-m4/board_info.txt
A src/mainboard/nec/945g-m4/cmos.default
A src/mainboard/nec/945g-m4/cmos.layout
A src/mainboard/nec/945g-m4/cstates.c
A src/mainboard/nec/945g-m4/devicetree.cb
A src/mainboard/nec/945g-m4/dsdt.asl
A src/mainboard/nec/945g-m4/gpio.c
A src/mainboard/nec/945g-m4/hda_verb.c
A src/mainboard/nec/945g-m4/romstage.c
A src/mainboard/nec/945g-m4/superio_hwm.c
A src/mainboard/nec/945g-m4/superio_hwm.h
A src/mainboard/nec/Kconfig
A src/mainboard/nec/Kconfig.name
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/raminit.c
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
41 files changed, 1,943 insertions(+), 145 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/25509/1
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 612b62e..7ca574b 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -19,6 +19,7 @@
source src/cpu/intel/model_f2x/Kconfig
source src/cpu/intel/model_f3x/Kconfig
source src/cpu/intel/model_f4x/Kconfig
+source src/cpu/intel/model_f6x/Kconfig
source src/cpu/intel/ep80579/Kconfig
source src/cpu/intel/haswell/Kconfig
# Sockets/Slots
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 59c3b8a..d8c7e72 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -165,6 +165,7 @@
while (microcode_len >= sizeof(*ucode_updates)) {
/* Newer microcode updates include a size field, whereas older
* containers set it at 0 and are exactly 2048 bytes long */
+ printk(BIOS_SPEW, "found microcode for sig=0x%x\n", ucode_updates->sig);
if (ucode_updates->total_size) {
update_size = ucode_updates->total_size;
} else {
diff --git a/src/cpu/intel/model_f6x/Kconfig b/src/cpu/intel/model_f6x/Kconfig
new file mode 100644
index 0000000..ede6a4a
--- /dev/null
+++ b/src/cpu/intel/model_f6x/Kconfig
@@ -0,0 +1,8 @@
+config CPU_INTEL_MODEL_F6X
+ bool
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_VERSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select SMP
+ select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_f6x/Makefile.inc b/src/cpu/intel/model_f6x/Makefile.inc
new file mode 100644
index 0000000..0e3ec50
--- /dev/null
+++ b/src/cpu/intel/model_f6x/Makefile.inc
@@ -0,0 +1,3 @@
+ramstage-y += model_f6x_init.c
+
+cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f6x/microcode.bin
diff --git a/src/cpu/intel/model_f6x/model_f6x_init.c b/src/cpu/intel/model_f6x/model_f6x_init.c
new file mode 100644
index 0000000..496f563
--- /dev/null
+++ b/src/cpu/intel/model_f6x/model_f6x_init.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+
+static void model_f6x_init(struct device *cpu)
+{
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+
+ if (!intel_ht_sibling()) {
+ /* MTRRs are shared between threads */
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+
+ /* Update the microcode */
+ intel_update_microcode_from_cbfs();
+ }
+
+ /* Enable the local CPU APICs */
+ setup_lapic();
+
+ /* Start up my CPU siblings */
+ intel_sibling_init(cpu);
+};
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_f6x_init,
+};
+
+static const struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x0f62 },
+ { X86_VENDOR_INTEL, 0x0f64 },
+ { X86_VENDOR_INTEL, 0x0f65 },
+ { X86_VENDOR_INTEL, 0x0f68 },
+ { 0, 0 },
+};
+
+static const struct cpu_driver model_f6x __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8b227bd..0d0cd00 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -8,7 +8,7 @@
select CPU_INTEL_MODEL_6FX
select CPU_INTEL_MODEL_F3X
select CPU_INTEL_MODEL_F4X
-# select CPU_INTEL_MODEL_F6X
+ select CPU_INTEL_MODEL_F6X
# select CPU_INTEL_MODEL_1066X
select CPU_INTEL_MODEL_1067X
select MMX
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
index ffcd1cb..8eef023 100644
--- a/src/cpu/intel/socket_LGA775/Makefile.inc
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -1,7 +1,7 @@
subdirs-y += ../model_6fx
subdirs-y += ../model_f3x
subdirs-y += ../model_f4x
-#subdirs-y += ../model_f6x
+subdirs-y += ../model_f6x
#subdirs-y += ../model_1066x
subdirs-y += ../model_1067x
subdirs-y += ../../x86/tsc
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 73b7431..4cdde3a 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -49,9 +49,22 @@
*/
static int get_fsb(void)
{
- const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
+ u32 fsbcode;
+ struct cpuinfo_x86 c;
+
+ get_fms(&c, cpuid_eax(1));
+ if ((c.x86) == 0xf && (c.x86_model) >= 2)
+ fsbcode = (rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 16) & 7;
+ else
+ fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
+
switch (fsbcode) {
- case 0: return 800; /* / 3 == 266 */
+ case 0:
+ if ((c.x86) == 0xf && (c.x86_model) == 2) {
+ return 300; /* / 3 == 100 */
+ } else {
+ return 800; /* / 3 == 266 */
+ }
case 1: return 400; /* / 3 == 133 */
case 2: return 600; /* / 3 == 200 */
case 3: return 500; /* / 3 == 166 */
@@ -128,16 +141,16 @@
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
numcpus, cores_per_package);
-
+if (0) {
num_cstates = get_cst_entries(&cstates);
speedstep_gen_pstates(&pstates);
+}
if (((cpuid_eax(1) >> 4) & 0xffff) == 0x1067)
/* For Penryn use HW_ALL. */
coordination = HW_ALL;
else
/* Use SW_ANY as that was the default. */
coordination = SW_ANY;
-
for (cpuID = 0; cpuID < numcpus; ++cpuID) {
for (coreID = 1; coreID <= cores_per_package; coreID++) {
if (coreID > 1) {
@@ -151,6 +164,7 @@
pcontrol_blk, plen);
/* Generate p-state entries. */
+if (0) {
gen_pstate_entries(&pstates, cpuID,
cores_per_package, coordination);
@@ -158,6 +172,7 @@
if (num_cstates > 0)
acpigen_write_CST_package(
cstates, num_cstates);
+}
acpigen_pop_len();
}
diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c
index 441f2a3..d87b8bb 100644
--- a/src/cpu/intel/speedstep/speedstep.c
+++ b/src/cpu/intel/speedstep/speedstep.c
@@ -30,19 +30,21 @@
static void speedstep_get_limits(sst_params_t *const params)
{
msr_t msr;
-
+printk(BIOS_INFO,"avant const ... \n");
const uint16_t cpu_id = (cpuid_eax(1) >> 4) & 0xffff;
+printk(BIOS_INFO,"state_mask ... \n");
const uint32_t state_mask =
/* Penryn supports non integer (i.e. half) ratios. */
((cpu_id == 0x1067) ? SPEEDSTEP_RATIO_NONINT : 0)
| SPEEDSTEP_RATIO_VALUE_MASK | SPEEDSTEP_VID_MASK;
-
+printk(BIOS_INFO,"avant memeset ... \n");
/* Initialize params to zero. */
memset(params, '\0', sizeof(*params));
-
+printk(BIOS_INFO,"avant if read msr truc ... \n");
/* Read Super-LFM parameters. */
if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and
enabled bits */
+printk(BIOS_INFO,"if MSR_EXTENDED_CONFIG... \n");
msr = rdmsr(MSR_FSB_CLOCK_VCC);
params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask);
params->slfm.dynfsb = 1;
@@ -50,6 +52,7 @@
}
/* Read normal minimum parameters. */
+printk(BIOS_INFO,"vers MSR_THERM2_CTL... \n");
msr = rdmsr(MSR_THERM2_CTL);
params->min = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask);
@@ -57,6 +60,7 @@
/* Newer CPUs provide the normal maximum settings in
IA32_PLATFORM_ID. The values in IA32_PERF_STATUS change
when using turbo mode. */
+printk(BIOS_INFO,"vers PLATFORM_ID... \n");
msr = rdmsr(IA32_PLATFORM_ID);
params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask);
if (cpu_id == 0x006e) {
@@ -98,12 +102,15 @@
/* Merom */
default:
/* Use Merom values by default (as before). */
+printk(BIOS_INFO,"default ... \n");
params->slfm.power = SPEEDSTEP_SLFM_POWER_MEROM;
params->min.power = SPEEDSTEP_MIN_POWER_MEROM;
params->max.power = SPEEDSTEP_MAX_POWER_MEROM;
params->turbo.power = SPEEDSTEP_MAX_POWER_MEROM;
+printk(BIOS_INFO,"end default ... \n");
break;
}
+printk(BIOS_INFO,"end switch ... \n");
}
/**
@@ -116,8 +123,9 @@
{
sst_params_t params;
/* Gather speedstep limits. */
+printk(BIOS_INFO,"vers speedstep_get_limits \n");
speedstep_get_limits(¶ms);
-
+printk(BIOS_INFO,"speedstep_get_limits ok \n");
/*\ First, find the number of normal states: \*/
@@ -136,6 +144,7 @@
do {
step2 += 2 * 2; /* Must be a multiple of 2 (doubled). */
states = ratio_diff2 / step2 + 1;
+printk(BIOS_INFO,"boucle DO \n");
} while (states > SPEEDSTEP_MAX_NORMAL_STATES);
if (step2 > 4)
printk(BIOS_INFO, "Enhanced Speedstep processor with "
@@ -143,15 +152,16 @@
SPEEDSTEP_MAX_NORMAL_STATES);
if (states < 2) /* Report at least two normal states. */
states = 2;
-
+printk(BIOS_INFO," states =2 .... \n");
/*\ Now, fill the table: \*/
table->num_states = 0;
-
+printk(BIOS_INFO," vers params.turbo .... \n");
/* Add turbo state if supported. */
if (params.turbo.is_turbo)
table->states[table->num_states++] = params.turbo;
+printk(BIOS_INFO," if params.turbo ....ok \n");
/* Add HFM first. */
table->states[table->num_states] = params.max;
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index eefb569..921679c 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -572,11 +572,11 @@
/* SDRAM Supported Burst length */
printram(" Burst length :");
- if (spd[16] & 0x06) {
+ if (spd[16] & 0x08) {
dimm->flags.bl8 = 1;
printram(" BL8");
}
- if (spd[22] & 0x04) {
+ if (spd[16] & 0x04) {
dimm->flags.bl4 = 1;
printram(" BL4");
}
diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig
new file mode 100644
index 0000000..e9ea87f
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Kconfig
@@ -0,0 +1,40 @@
+if BOARD_NEC_945G_M4
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627EHG
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_512
+ select CHANNEL_XOR_RANDOMIZATION
+ #select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+
+config MAINBOARD_DIR
+ string
+ default nec/945g-m4
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "945G-M4"
+
+#config MMCONF_BASE_ADDRESS
+# hex
+# default 0xf0000000
+
+#config IRQ_SLOT_COUNT
+# int
+# default 18
+
+config MAX_CPUS
+ int
+ default 4
+
+endif # BOARD_NEC_945G_M4
diff --git a/src/mainboard/nec/945g-m4/Kconfig.name b/src/mainboard/nec/945g-m4/Kconfig.name
new file mode 100644
index 0000000..9ad86ba
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_NEC_945G_M4
+ bool "945G-M4"
diff --git a/src/mainboard/nec/945g-m4/Makefile.inc b/src/mainboard/nec/945g-m4/Makefile.inc
new file mode 100644
index 0000000..3f072f5
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/Makefile.inc
@@ -0,0 +1,3 @@
+ramstage-y += superio_hwm.c
+ramstage-y += cstates.c
+romstage-y += gpio.c
diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl
new file mode 100644
index 0000000..8f20f9d
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ec.asl
@@ -0,0 +1 @@
+//to make the compiler happy
diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000..5327b3e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* This is board specific information: IRQ routing for i945G */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, 0, 10 },
+ Package() { 0x0001ffff, 1, 0, 11 },
+ Package() { 0x0001ffff, 2, 0, 12 },
+ Package() { 0x0001ffff, 3, 0, 13 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 10 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 10 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 10 },
+ Package() { 0x001cffff, 1, 0, 11 },
+ Package() { 0x001cffff, 2, 0, 12 },
+ Package() { 0x001cffff, 3, 0, 13 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, 0, 17 },
+ Package() { 0x001dffff, 1, 0, 19 },
+ Package() { 0x001dffff, 2, 0, 13 },
+ Package() { 0x001dffff, 3, 0, 12 },
+ // AC97/IDE 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, 0, 11 },
+ Package() { 0x001effff, 1, 0, 24 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, 0, 12 },
+ Package() { 0x001fffff, 1, 0, 13 },
+ })
+ } Else {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ // AC97/IDE 0:1e.2, 0:1e.3
+ Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..590f6b3
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 16},
+
+ Package() { 0x0001ffff, 0, 0, 20},
+ Package() { 0x0001ffff, 1, 0, 21},
+ Package() { 0x0001ffff, 2, 0, 22},
+ Package() { 0x0001ffff, 3, 0, 23},
+
+ Package() { 0x0002ffff, 0, 0, 21},
+ Package() { 0x0002ffff, 1, 0, 22},
+ Package() { 0x0002ffff, 2, 0, 23},
+ Package() { 0x0002ffff, 3, 0, 20},
+
+ Package() { 0x0003ffff, 0, 0, 22},
+ Package() { 0x0003ffff, 1, 0, 23},
+ Package() { 0x0003ffff, 2, 0, 20},
+ Package() { 0x0003ffff, 3, 0, 21},
+
+ Package() { 0x0004ffff, 0, 0, 23},
+ Package() { 0x0004ffff, 1, 0, 20},
+ Package() { 0x0004ffff, 2, 0, 21},
+ Package() { 0x0004ffff, 3, 0, 22},
+
+ Package() { 0x0005ffff, 0, 0, 19},
+ Package() { 0x0005ffff, 1, 0, 18},
+ Package() { 0x0005ffff, 2, 0, 17},
+ Package() { 0x0005ffff, 3, 0, 16},
+
+ Package() { 0x0006ffff, 0, 0, 18},
+ Package() { 0x0006ffff, 1, 0, 17},
+ Package() { 0x0006ffff, 2, 0, 16},
+ Package() { 0x0006ffff, 3, 0, 19},
+
+ Package() { 0x0009ffff, 0, 0, 21},
+ Package() { 0x0009ffff, 1, 0, 22},
+ Package() { 0x0009ffff, 2, 0, 23},
+ Package() { 0x0009ffff, 3, 0, 20},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
+
+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+ Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+ Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+ Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+ Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+ })
+}
diff --git a/src/mainboard/nec/945g-m4/acpi/mainboard.asl b/src/mainboard/nec/945g-m4/acpi/mainboard.asl
new file mode 100644
index 0000000..0454c3f
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (SLPB)
+{
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl
new file mode 100644
index 0000000..6a05ab9
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/platform.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Call a trap so SMI can prepare for Sleep as well.
+ // TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/superio.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl
new file mode 100644
index 0000000..ea47ff4
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+
+ // FIXME these could/should be read from the
+ // GNVS area, so they can be controlled by
+ // coreboot
+ Name(TC1V, 0x04)
+ Name(TC2V, 0x03)
+ Name(TSPV, 0x64)
+
+ // At which temperature should the OS start
+ // active cooling?
+ Method (_AC0, 0, Serialized)
+ {
+ Return (0xf5c) // Value for Rocky
+ }
+
+ // Method (_AC1, 0, Serialized)
+ // {
+ // Return (0xf5c)
+ // }
+
+ // Critical shutdown temperature
+ Method (_CRT, 0, Serialized)
+ {
+ Return (Add (0x0aac, 0x50)) // FIXME
+ }
+
+ // CPU throttling start temperature
+ Method (_PSV, 0, Serialized)
+ {
+ Return (0xaaf) // FIXME
+ }
+
+ // Get DTS Temperature
+ Method (_TMP, 0, Serialized)
+ {
+ Return (0xaac) // FIXME
+ }
+
+ // Processors used for active cooling
+ Method (_PSL, 0, Serialized)
+ {
+ If (MPEN) {
+ Return (Package() {\_PR.CPU1, \_PR.CPU2})
+ }
+ Return (Package() {\_PR.CPU1})
+ }
+
+ // TC1 value for passive cooling
+ Method (_TC1, 0, Serialized)
+ {
+ Return (TC1V)
+ }
+
+ // TC2 value for passive cooling
+ Method (_TC2, 0, Serialized)
+ {
+ Return (TC2V)
+ }
+
+ // Sampling period for passive cooling
+ Method (_TSP, 0, Serialized)
+ {
+ Return (TSPV)
+ }
+
+
+ }
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl
new file mode 100644
index 0000000..5695001
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi/video.asl
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c
new file mode 100644
index 0000000..d87fef5
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/acpi_tables.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+
+#include "southbridge/intel/i82801gx/nvs.h"
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}
diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt
new file mode 100644
index 0000000..b13671a
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=default&source=1409
+ROM package: PLCC
+ROM protocol: FWH
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/nec/945g-m4/cmos.default b/src/mainboard/nec/945g-m4/cmos.default
new file mode 100644
index 0000000..ff1367e
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/cmos.default
@@ -0,0 +1,7 @@
+boot_option=Fallback
+baud_rate=115200
+debug_level=Spew
+hyper_threading=Enable
+nmi=Enable
+boot_devices=''
+#gfx_uma_size=8M
diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout
new file mode 100644
index 0000000..37e387d
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/cmos.layout
@@ -0,0 +1,188 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 3 e 11 gfx_uma_size
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+#928 40 r 0 unused
+
+# coreboot config options: mainboard specific options
+948 2 e 8 cpufan_cruise_control
+950 2 e 8 sysfan_cruise_control
+952 4 e 9 cpufan_speed
+#956 4 e 10 cpufan_temperature
+960 4 e 9 sysfan_speed
+#964 4 e 10 sysfan_temperature
+
+968 1 e 2 ethernet1
+#969 1 e 2 ethernet2
+#970 1 e 2 ethernet3
+
+#971 13 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# ram initialization internal data
+1024 8 r 0 C0WL0REOST
+1032 8 r 0 C1WL0REOST
+1040 8 r 0 RCVENMT
+1048 4 r 0 C0DRT1
+1052 4 r 0 C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# Fan Cruise Control
+8 0 Disabled
+8 1 Speed
+#8 2 Thermal
+# Fan Speed (Rotations per Minute)
+9 0 5625
+9 1 5192
+9 2 4753
+9 3 4326
+9 4 3924
+9 5 3552
+9 6 3214
+9 7 2909
+9 8 2636
+9 9 2393
+9 10 2177
+9 11 1985
+9 12 1814
+9 13 1662
+9 14 1527
+9 15 1406
+#
+# Temperature (°C/°F)
+#10 0 30/86
+#10 1 33/91
+#10 2 36/96
+#10 3 39/102
+#10 4 42/107
+#10 5 45/113
+#10 6 48/118
+#10 7 51/123
+#10 8 54/129
+#10 9 57/134
+#10 10 60/140
+#10 11 63/145
+#10 12 66/150
+#10 13 69/156
+#10 14 72/161
+#10 15 75/167
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/nec/945g-m4/cstates.c b/src/mainboard/nec/945g-m4/cstates.c
new file mode 100644
index 0000000..03a8dcd
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/cstates.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <arch/x86/include/arch/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
\ No newline at end of file
diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb
new file mode 100644
index 0000000..06df7cf
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/devicetree.cb
@@ -0,0 +1,159 @@
+chip northbridge/intel/i945
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ end
+ device domain 0 on
+# pci_mmio_size = 1024
+ device pci 00.0 on end # [8086:2770]
+ device pci 01.0 on # [8086:2771]
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 02.0 on # [8086:2772]
+ ioapic_irq 2 INTA 0x10
+ end
+ chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x86"
+ register "pirqd_routing" = "0x85"
+ register "pirqe_routing" = "0x83"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x85"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi13_routing" = "1"
+ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0"
+
+ device pci 1b.0 off # [8086:27d8]
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1c.0 on # [8086:27d0]
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1c.2 off # [8086:27d4]
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1c.3 off # [8086:27d6]
+ ioapic_irq 2 INTD 0x13
+ end
+ device pci 1d.0 on # [8086:27c8]
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1d.1 on # [8086:27c9]
+ ioapic_irq 2 INTB 0x11
+ end
+ device pci 1d.2 on # [8086:27ca]
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1d.3 on # [8086:27cb]
+ ioapic_irq 2 INTD 0x13
+ end
+ device pci 1d.7 on # [8086:27cc]
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1e.0 on # [8086:244e]
+ end
+ device pci 1e.2 on # [8086:27de]
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1f.0 on # [8086:27b8]
+ ioapic_irq 2 INTA 0x10
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ chip superio/winbond/w83627ehg # Super I/O Winbond
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+
+ device pnp 2e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+
+ device pnp 2e.3 off # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 0x0c
+ end
+
+ device pnp 2e.106 off # Serial flash interface
+ end
+ device pnp 2e.007 on # GPIO 1
+ io 0x62 = 0x330
+ end
+ device pnp 2e.107 off # Game port
+ io 0x60 = 0x201
+ end
+ device pnp 2e.207 on # MIDI
+ io 0x62 = 0x330
+ irq 0x70 = 0x9
+ end
+ device pnp 2e.307 on # GPIO 6
+ end
+ device pnp 2e.8 off end # WDTO#, PLED
+
+ device pnp 2e.009 on # GPIO 2
+ end
+ device pnp 2e.109 on # GPIO 3
+ irq 0xf0 = 0x8c
+ end
+
+ device pnp 2e.209 on # GPIO 4
+ irq 0xf5 = 0xf8
+ end
+
+ device pnp 2e.309 on # GPIO 5
+ irq 0xe0 = 0xdf
+ end
+
+ device pnp 2e.a on # ACPI
+ irq 0x70 = 0
+ end
+
+ device pnp 2e.b on # Hardware monitor
+ io 0x60 = 0x290 #0a10
+ irq 0x70 = 0
+ end
+
+ end # Winbond
+ end # LPC
+ device pci 1f.1 on # [8086:27df]
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1f.2 on # [8086:27c0]
+ ioapic_irq 2 INTB 0x11
+ end
+ device pci 1f.3 on # [8086:27da]
+ ioapic_irq 2 INTB 0x11
+ end
+ #device pci 02:00.0 on #[10ec/8168]
+ # ioapic_irq 2 INTA 0x10
+ #end
+ #vendor bios device pci 1c.0 on end # PCI Express Gigabit Ethernet Controller [10ec:8168]
+ end # i82801gx
+ end # domain 0
+end
diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl
new file mode 100644
index 0000000..5c55245
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/dsdt.asl
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock (
+ "dsdt.aml",
+ "DSDT",
+ 0x02,
+ "COREv4",
+ "COREBOOT",
+ 0x00000108
+)
+{
+ // Some generic macros
+ // #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ //#include "acpi/thermal.asl"
+
+ #include <cpu/intel/speedstep/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/i945/acpi/i945.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/nec/945g-m4/gpio.c b/src/mainboard/nec/945g-m4/gpio.c
new file mode 100644
index 0000000..3477e40
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/gpio.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_OUTPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio16 = GPIO_LEVEL_HIGH,
+ .gpio17 = GPIO_LEVEL_HIGH,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_HIGH,
+ .gpio25 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio1 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio9 = GPIO_INVERT,
+ .gpio10 = GPIO_INVERT,
+ .gpio11 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+};
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/nec/945g-m4/hda_verb.c b/src/mainboard/nec/945g-m4/hda_verb.c
new file mode 100644
index 0000000..9c8c7c4
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/hda_verb.c
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[0] = {};
+const u32 pc_beep_verbs[0] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c
new file mode 100644
index 0000000..e0e0544
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/romstage.c
@@ -0,0 +1,288 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2014 coreboot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/romstage.h>
+#include <lib.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include <timestamp.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627ehg/w83627ehg.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <halt.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
+#include <arch/cpu.h>
+#include <security/tpm/tis.h>
+
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+#define DUMMY_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
+#define GPIO_MIDI_DEV PNP_DEV(0x2e, W83627EHG_GPIO_GAME_MIDI_V)
+#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
+#define HWM_DEV PNP_DEV(0x2e, W83627EHG_HWM)
+//#define TCOBASE (PMBASE + 0x60)
+
+static void ich7_enable_lpc(void)
+{
+ // Enable Serial IRQ
+ pci_write_config8(LPC_DEV, 0x64, 0xd0);
+ // LPC I/O decode range
+ pci_write_config16(LPC_DEV, 0x80, 0x0010);
+ // LPC Interface Enables
+ pci_write_config16(LPC_DEV, 0x82 /*LPC_EN*/, COMA_LPC_EN | LPT_LPC_EN |
+ FDD_LPC_EN | KBC_LPC_EN |CNF1_LPC_EN |CNF2_LPC_EN);
+ // GEN1_DEC. LPC interface generic decode Rang1
+ pci_write_config32(LPC_DEV, 0x84, 0x007c0291);
+ // GEN2_DEC. LPC interface generic decode Rang2 - TPM ?
+ pci_write_config32(LPC_DEV, 0x88, 0x007c3f91);
+}
+
+static int sio_init(u8 bsel)
+{
+ int need_reset = 0;
+ u8 reg, old_reg;
+
+ pnp_enter_conf_state(DUMMY_DEV);
+ pnp_write_config(DUMMY_DEV, 0x24, 0x44);
+ pnp_write_config(DUMMY_DEV, 0x29, 0x05);
+
+ reg = 0x82;
+ old_reg = pnp_read_config(DUMMY_DEV, 0x2c);
+ pnp_write_config(DUMMY_DEV, 0x2c, reg);
+ need_reset = (reg != old_reg);
+
+ pnp_write_config(DUMMY_DEV, 0x2d, 0x20);
+ pnp_exit_conf_state(DUMMY_DEV);
+
+ pnp_enter_conf_state(ACPI_DEV);
+ pnp_set_logical_device(ACPI_DEV);
+ pnp_write_config(ACPI_DEV, 0x30, 0x01);
+ // Read-Clear
+// reg = pnp_read_config(ACPI_DEV, 0xe3);
+ pnp_exit_conf_state(ACPI_DEV);
+
+ // GPIO1, GPIO6, game port, MIDI
+ pnp_enter_conf_state(GPIO_MIDI_DEV);
+ pnp_set_logical_device(GPIO_MIDI_DEV);
+ pnp_write_config(GPIO_MIDI_DEV, 0x30, 0x01);
+ pnp_write_config(GPIO_MIDI_DEV, 0x60, 0x00);
+ pnp_write_config(GPIO_MIDI_DEV, 0x61, 0x00);
+ pnp_write_config(GPIO_MIDI_DEV, 0x62, 0x00);
+ pnp_write_config(GPIO_MIDI_DEV, 0x63, 0x00);
+ pnp_write_config(GPIO_MIDI_DEV, 0x70, 0x00);
+ pnp_write_config(GPIO_MIDI_DEV, 0xf0, 0x5f);
+ pnp_write_config(GPIO_MIDI_DEV, 0xf1, 0x5f);
+ pnp_write_config(GPIO_MIDI_DEV, 0xf5, 0xff);
+ pnp_write_config(GPIO_MIDI_DEV, 0xf6, 0xff);
+ pnp_exit_conf_state(GPIO_MIDI_DEV);
+
+ // GPIO2, GPIO3, GPIO4, GPIO5, SUSLED
+ pnp_enter_conf_state(GPIO_DEV);
+ pnp_set_logical_device(GPIO_DEV);
+ pnp_write_config(GPIO_DEV, 0x30, 0x0e);
+ pnp_write_config(GPIO_DEV, 0xe0, 0xdf);
+ pnp_write_config(GPIO_DEV, 0xe2, 0x20);
+ pnp_write_config(GPIO_DEV, 0xe4, 0xff);
+ pnp_write_config(GPIO_DEV, 0xe5, 0xff);
+ pnp_write_config(GPIO_DEV, 0xf0, 0x8c);
+ pnp_write_config(GPIO_DEV, 0xf2, 0x00);
+
+ //reg = (bsel & 3) << 2;
+ //old_reg = pnp_read_config(GPIO_DEV, 0xf1);
+ pnp_write_config(GPIO_DEV, 0xf1, 0x8c);
+ //need_reset += (reg != old_reg);
+
+ //reg = (bsel >> 2) << 5;
+ //old_reg = pnp_read_config(GPIO_DEV, 0xe1);
+ pnp_write_config(GPIO_DEV, 0xe1, 0);
+ //need_reset += ((reg & 0x20) != (old_reg & 0x20));
+ pnp_exit_conf_state(GPIO_DEV);
+
+ // Enable HWM
+ pnp_enter_conf_state(HWM_DEV);
+ pnp_set_logical_device(HWM_DEV);
+ pnp_set_iobase(HWM_DEV, PNP_IDX_IO0, 0x290);
+ pnp_write_config(HWM_DEV, 0x30, 0x01);
+ pnp_exit_conf_state(HWM_DEV);
+
+ return need_reset;
+}
+
+static u8 msr_get_fsb(void)
+{
+ u8 fsbcfg;
+ msr_t msr;
+ const u32 eax = cpuid_eax(1);
+
+ /* Netburst */
+ if (((eax >> 8) & 0xf) == 0xf) {
+ msr = rdmsr(MSR_EBC_FREQUENCY_ID);
+ fsbcfg = (msr.lo >> 16) & 0x7;
+ } else { /* Intel Core 2 */
+ msr = rdmsr(MSR_FSB_FREQ);
+ fsbcfg = msr.lo & 0x7;
+ }
+
+ return fsbcfg;
+}
+
+static void rcba_config(void)
+{
+ /* Enable IOAPIC */
+ RCBA8(OIC) = 0x03;
+
+ /* Disable unused devices */
+ RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 |
+ FD_HDAUD;
+
+ /* Enable PCIe Root Port Clock Gate */
+ RCBA32(CG) = 0x00000001;
+}
+
+static void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+ printk(BIOS_DEBUG, "program secondary mlt XXX byte \n");
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+printk(BIOS_DEBUG, "reset rtc power status \n");
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+printk(BIOS_DEBUG, "usb transient disconnect \n");
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+ // enable AC '97
+ pci_write_config8(PCI_DEV(0, 0x1e, 2), 0x41, 1);
+ pci_write_config32(PCI_DEV(0, 0x1e, 2), 0x10, 0x1800);
+ pci_write_config32(PCI_DEV(0, 0x1e, 2), 0x14, 0x1900);
+ pci_write_config8(PCI_DEV(0, 0x1e, 2), 0x4, 1);
+
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ RCBA32(0x0214) = 0x10030549;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(0x3418) |= (1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ int s3resume = 0, boot_mode = 0;
+
+ u8 c_bsel = msr_get_fsb();
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ if (bist == 0)
+ enable_lapic();
+
+ ich7_enable_lpc();
+
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE /* 0x3f8*/);
+ /* Set up the console */
+ console_init();
+ printk(BIOS_DEBUG, "console init done.\n");
+
+ report_bist_failure(bist);
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected.\n");
+ boot_mode = 1;
+ }
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+
+ i945_early_initialization();
+ s3resume = southbridge_detect_s3_resume();
+
+ /* copy of asus/p5gc-mx .... for test
+ * Result is that FSB is incorrect on s3 resume (fixed at 800MHz).
+ * Some CPU accept this others don't.
+ */
+ if (!s3resume && sio_init(c_bsel)) {
+ printk(BIOS_DEBUG,
+ "Needs reset to configure CPU BSEL straps\n");
+ outb(0xe, 0xcf9);
+ halt();
+ }
+
+printk(BIOS_DEBUG, "Enable SPD ROMs and DDR-II DRAM \n");
+ enable_smbus();
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+ dump_spd_registers();
+#endif
+ timestamp_add_now(TS_BEFORE_INITRAM);
+ sdram_initialize(s3resume ? 2 : boot_mode, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
+ printk(BIOS_DEBUG, "Perform some initialization that must run before stage2 \n");
+ early_ich7_init();
+
+ rcba_config();
+ printk(BIOS_DEBUG, "Chipset Errata! \n");
+ fixup_i945_errata();
+
+ printk(BIOS_DEBUG, "Initialize the internal PCIe links before we go into stage2 \n");
+ i945_late_initialization(s3resume);
+// sdram_dump_mchbar_registers();
+// dump_pci_devices();
+
+#if IS_ENABLED(CONFIG_LPC_TPM)
+ init_tpm(s3resume);
+#endif
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c
new file mode 100644
index 0000000..a876d78
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.c
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <pc80/mc146818rtc.h>
+
+#include "superio_hwm.h"
+
+/* Hardware Monitor */
+
+#define FAN_CRUISE_CONTROL_DISABLED 0
+#define FAN_CRUISE_CONTROL_SPEED 1
+#define FAN_CRUISE_CONTROL_THERMAL 2
+
+#define FAN_SPEED_5625 0
+//#define FAN_TEMPERATURE_30DEGC 0
+
+#define HWM_BASE 0x290 //0x0a10
+
+static void hwm_write(u8 reg, u8 value)
+{
+ outb(reg, HWM_BASE + 0x05); // Index port
+ outb(value, HWM_BASE + 0x06); // Data port
+}
+
+static void hwm_bank(u8 bank)
+{
+ hwm_write(0x4e, bank);
+}
+
+struct fan_speed {
+ u8 fan_in;
+ u16 fan_speed;
+};
+
+// FANIN Target Speed Register
+// FANIN = 337500 / RPM
+struct fan_speed fan_speeds[] = {
+ { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
+ { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
+ { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 },
+ { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 }
+};
+
+struct temperature {
+ u8 deg_celsius;
+ u8 deg_fahrenheit;
+};
+
+struct temperature temperatures[] = {
+ { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 },
+ { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 },
+ { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 },
+ { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 }
+};
+
+void hwm_setup(void)
+{
+ int cpufan_control = 0, sysfan_control = 0;
+ int cpufan_speed = 0, sysfan_speed = 0;
+ int cpufan_temperature = 0, sysfan_temperature = 0;
+
+ if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS)
+ cpufan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS)
+ cpufan_speed = FAN_SPEED_5625;
+ //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS)
+ // cpufan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS)
+ sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
+ if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS)
+ sysfan_speed = FAN_SPEED_5625;
+ //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS)
+ // sysfan_temperature = FAN_TEMPERATURE_30DEGC;
+
+ // hwm_write(0x31, 0x20); // AVCC high limit
+ // hwm_write(0x34, 0x06); // VIN2 low limit
+
+ hwm_bank(0);
+ hwm_write(0x59, 0x20); // Diode Selection
+ hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
+
+ hwm_bank(4);
+ hwm_write(0x54, 0xf1); // SYSTIN temperature offset
+ hwm_write(0x55, 0x19); // CPUTIN temperature offset
+ hwm_write(0x56, 0xfc); // AUXTIN temperature offset
+
+ hwm_bank(0x80); // Default
+
+ u8 fan_config = 0;
+ // 00 FANOUT is Manual Mode
+ // 01 FANOUT is Thermal Cruise Mode
+ // 10 FANOUT is Fan Speed Cruise Mode
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
+ }
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break;
+ case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
+ }
+ // This register must be written first
+ hwm_write(0x04, fan_config);
+
+ switch (cpufan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
+ fan_speeds[cpufan_speed].fan_speed);
+ hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
+ temperatures[cpufan_temperature].deg_celsius,
+ temperatures[cpufan_temperature].deg_fahrenheit);
+ hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature
+ break;
+ }
+
+ switch (sysfan_control) {
+ case FAN_CRUISE_CONTROL_SPEED:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
+ fan_speeds[sysfan_speed].fan_speed);
+ hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed
+ break;
+ case FAN_CRUISE_CONTROL_THERMAL:
+ printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
+ temperatures[sysfan_temperature].deg_celsius,
+ temperatures[sysfan_temperature].deg_fahrenheit);
+ hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
+ break;
+ }
+
+ hwm_write(0x0e, 0x02); // Fan Output Step Down Time
+ hwm_write(0x0f, 0x02); // Fan Output Step Up Time
+
+ hwm_write(0x47, 0xaf); // FAN divisor register
+ hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
+
+ hwm_write(0x40, 0x01); // Init, but no SMI#
+}
diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h
new file mode 100644
index 0000000..c69ebc8
--- /dev/null
+++ b/src/mainboard/nec/945g-m4/superio_hwm.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_HWM_H
+#define SUPERIO_HWM_H
+
+void hwm_setup(void);
+
+#endif /* SUPERIO_HWM_H */
diff --git a/src/mainboard/nec/Kconfig b/src/mainboard/nec/Kconfig
new file mode 100644
index 0000000..b9b4114
--- /dev/null
+++ b/src/mainboard/nec/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_NEC
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/nec/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/nec/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "NEC"
+
+endif # VENDOR_NEC
diff --git a/src/mainboard/nec/Kconfig.name b/src/mainboard/nec/Kconfig.name
new file mode 100644
index 0000000..5f4f892
--- /dev/null
+++ b/src/mainboard/nec/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_NEC
+ bool "NEC"
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index bf486a0..61b7dc3 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -26,6 +26,7 @@
#include "i945.h"
#include <pc80/mc146818rtc.h>
#include <southbridge/intel/common/gpio.h>
+//#include <southbridge/intel/i82801gx/i82801gx.h>
int i945_silicon_revision(void)
{
@@ -157,13 +158,16 @@
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, /*(uintptr_t)DEFAULT_RCBA | 1*/0xfed1c001);
+printk(BIOS_DEBUG, "DEFAULT_PMBASE.. %06x\n", DEFAULT_PMBASE);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
+printk(BIOS_DEBUG, "2\n");
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */
-
+printk(BIOS_DEBUG, "DEFAULT_GPIOBASE:... %06x\n",DEFAULT_GPIOBASE);
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
+printk(BIOS_DEBUG, "..4\n");
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */
+printk(BIOS_DEBUG, "..5\n");
setup_pch_gpios(&mainboard_gpio_map);
printk(BIOS_DEBUG, " done.\n");
@@ -179,11 +183,15 @@
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
+printk(BIOS_DEBUG, " DEFAULT_EPBAR %06x\n", DEFAULT_EPBAR);
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+printk(BIOS_DEBUG, "n1 ");
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, /*(uintptr_t)DEFAULT_MCHBAR | 1*/0xfed14001);
+printk(BIOS_DEBUG, "n2");
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, /*(uintptr_t)DEFAULT_DMIBAR | 1*/0xfed18001);
+printk(BIOS_DEBUG, "n3");
pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
-
+ printk(BIOS_DEBUG, " ");
/* vram size from cmos option */
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS)
gfxsize = 2; /* 2 for 8MB */
@@ -191,7 +199,7 @@
if (gfxsize > 6)
gfxsize = 2;
pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4));
-
+ printk(BIOS_DEBUG, " ");
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b2348f5..7d61c22 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -632,43 +632,30 @@
static void sdram_program_dram_width(struct sys_info *sysinfo)
{
u16 c0dramw = 0, c1dramw = 0;
- int idx;
+ int i, idx;
if (sysinfo->dual_channel)
idx = 2;
else
idx = 1;
- switch (sysinfo->dimm[0]) {
- case SYSINFO_DIMM_X16DS:
- c0dramw = 0x0000; break;
- case SYSINFO_DIMM_X8DS:
- c0dramw = 0x0001; break;
- case SYSINFO_DIMM_X16SS:
- c0dramw = 0x0000; break;
- case SYSINFO_DIMM_X8DDS:
- c0dramw = 0x0005; break;
- case SYSINFO_DIMM_NOT_POPULATED:
- c0dramw = 0x0000; break;
+ for (i = 0; i < DIMM_SOCKETS; i++) { /* Channel A */
+ switch (sysinfo->dimm[i]) {
+ case SYSINFO_DIMM_X16DS: c0dramw |= (0x0000) << 4*(i % 2); break;
+ case SYSINFO_DIMM_X8DS: c0dramw |= (0x0001) << 4*(i % 2); break;
+ case SYSINFO_DIMM_X16SS: c0dramw |= (0x0000) << 4*(i % 2); break;
+ case SYSINFO_DIMM_X8DDS: c0dramw |= (0x0005) << 4*(i % 2); break;
+ case SYSINFO_DIMM_NOT_POPULATED: c0dramw |= (0x0000) << 4*(i % 2); break;
+ }
}
-
- switch (sysinfo->dimm[idx]) {
- case SYSINFO_DIMM_X16DS:
- c1dramw = 0x0000; break;
- case SYSINFO_DIMM_X8DS:
- c1dramw = 0x0010; break;
- case SYSINFO_DIMM_X16SS:
- c1dramw = 0x0000; break;
- case SYSINFO_DIMM_X8DDS:
- c1dramw = 0x0050; break;
- case SYSINFO_DIMM_NOT_POPULATED:
- c1dramw = 0x0000; break;
- }
-
- if (!sdram_capabilities_dual_channel()) {
- /* Single Channel */
- c0dramw |= c1dramw;
- c1dramw = 0;
+ for (i = DIMM_SOCKETS; i < idx * DIMM_SOCKETS; i++) { /* Channel B */
+ switch (sysinfo->dimm[i]) {
+ case SYSINFO_DIMM_X16DS: c1dramw |= (0x0000) << 4*(i % 2); break;
+ case SYSINFO_DIMM_X8DS: c1dramw |= (0x0001) << 4*(i % 2); break;
+ case SYSINFO_DIMM_X16SS: c1dramw |= (0x0000) << 4*(i % 2); break;
+ case SYSINFO_DIMM_X8DDS: c1dramw |= (0x0005) << 4*(i % 2); break;
+ case SYSINFO_DIMM_NOT_POPULATED: c1dramw |= (0x0000) << 4*(i % 2); break;
+ }
}
MCHBAR16(C0DRAMW) = c0dramw;
@@ -683,25 +670,25 @@
MCHBAR32(offset+(i*4)) = slew_rate_table[i];
}
-static const u32 dq2030[] = {
+static const u32 dq2030[] = { // ok
0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
};
-static const u32 dq2330[] = {
+static const u32 dq2330[] = { //ok
0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
};
-static const u32 cmd2710[] = {
- 0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
- 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
- 0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
- 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
+static const u32 cmd2710[] = { //ok
+ 0x00000000, 0x01000000, 0x02010101, 0x06050403,
+ 0x0b0a0807, 0x0f0e0d0c, 0x16141210, 0x1f1d1b19,
+ 0x00000000, 0x02010101, 0x04030302, 0x06050504,
+ 0x0a090807, 0x14100e0c, 0x1c1a1816, 0x1f1f1f1e
};
static const u32 cmd3210[] = {
@@ -714,15 +701,15 @@
static const u32 clk2030[] = {
0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211,
0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c,
- 0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120,
- 0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937
+ 0x09090808, 0x0c0b0b0a, 0x100f0e0d, 0x14131211,
+ 0x18171615, 0x1e1c1a19, 0x26242220, 0x2e2c2a28
};
static const u32 ctl3215[] = {
- 0x01010000, 0x03020101, 0x07060504, 0x0b0a0908,
- 0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19,
- 0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b,
- 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d
+ 0x07070606, 0x0e0c0a08, 0x17141210, 0x201e1c1a,
+ 0x28262422, 0x302e2c2a, 0x38363432, 0x3f3e3c3a,
+ 0x13131212, 0x16151414, 0x211d1a18, 0x28262422,
+ 0x302e2c2a, 0x38363432, 0x3f3e3c3a, 0x3f3f3f3f
};
static const u32 ctl3220[] = {
@@ -894,11 +881,11 @@
static const u8 dual_channel_strength_multiplier[] = {
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
- 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
- 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
- 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
- 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
- 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
+ 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x55, 0x44,
+ 0x44, 0x22, 0x00, 0x00, 0x33, 0x44, 0x22, 0x33,
+ 0x44, 0x22, 0x88, 0x33, 0x44, 0x22, 0x55, 0x33,
+ 0x44, 0x22, 0x00, 0x44, 0x33, 0x44, 0x44, 0x22,
+ 0x44, 0x22, 0x88, 0x33, 0x44, 0x22, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33,
0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00,
@@ -969,13 +956,17 @@
printk(BIOS_DEBUG, "Table Index: %d\n", idx);
MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
- MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
+// MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
MCHBAR8(G3SC) = strength_multiplier[idx * 8 + 2];
MCHBAR8(G4SC) = strength_multiplier[idx * 8 + 3];
MCHBAR8(G5SC) = strength_multiplier[idx * 8 + 4];
MCHBAR8(G6SC) = strength_multiplier[idx * 8 + 5];
- MCHBAR8(G7SC) = strength_multiplier[idx * 8 + 6];
- MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
+ MCHBAR8(G7SC) = strength_multiplier[idx * 8 /*+ 6 */];
+// MCHBAR8(G8SC) = strength_multiplier[idx * 8 + 7];
+// if (5 * sysinfo->dimm[0] + sysinfo->dimm[1])
+ MCHBAR8(G2SC) = strength_multiplier[idx * 8 + (5 * sysinfo->dimm[0] + sysinfo->dimm[1]) + 16];
+// if (5 * sysinfo->dimm[2] + sysinfo->dimm[3])
+ MCHBAR8(G8SC) = strength_multiplier[idx * 8 + (5 * sysinfo->dimm[2] + sysinfo->dimm[3]) + 32];
/* Channel 0 */
sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0));
@@ -1314,7 +1305,6 @@
if (sysinfo->banks[i] != 8)
continue;
-
printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
if (i & 1)
@@ -1413,7 +1403,15 @@
reg32 |= (1 << 2); /* Burst Length 8 */
reg32 &= ~((1 << 13) | (1 << 12));
MCHBAR32(C1DRC0) = reg32;
-
+//
+ reg32 = (1 << 14);
+ for (i = 0; i < 2 * DIMM_SOCKETS; i++) {
+ if (sysinfo->dimm[i] == 1)
+ reg32 = 0;
+ }
+ MCHBAR32(C0DRC0) |= reg32;
+ MCHBAR32(C1DRC0) |= reg32;
+//
if (!sysinfo->dual_channel && sysinfo->dimm[1] !=
SYSINFO_DIMM_NOT_POPULATED) {
reg32 = MCHBAR32(C0DRC0);
@@ -1630,6 +1628,8 @@
MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
case 667:
MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
+ case 800:
+ MCHBAR8(CPCTL) = 0x02; break; /* FSB800 */
}
MCHBAR16(CPCTL) &= ~(1 << 11);
@@ -2460,11 +2460,15 @@
if (!(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) {
- printk(BIOS_DEBUG, "one dimm per channel config..\n");
+ printk(BIOS_DEBUG, "Channel 0 have one DIMM config..\n");
reg32 = MCHBAR32(C0ODT);
reg32 &= ~(7 << 28);
MCHBAR32(C0ODT) = reg32;
+ }
+ if ( !(sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED &&
+ sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) ) {
+ printk(BIOS_DEBUG, "Channel 1 have one DIMM config..\n");
reg32 = MCHBAR32(C1ODT);
reg32 &= ~(7 << 28);
MCHBAR32(C1ODT) = reg32;
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 3dcfc24..594959a 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -1006,7 +1006,7 @@
size = ARRAY_SIZE(baytrail_score_ssus_gpio_registers);
break;
case PCI_DEVICE_ID_INTEL_CM236:
- print_gpio_groups(sb);
+ print_gpio_groups(sb, false);
return 0;
case PCI_DEVICE_ID_INTEL_82371XX:
printf("This southbridge has GPIOs in the PM unit.\n");
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index 11f6808..69b659f 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -17,6 +17,7 @@
#include <stdlib.h>
#include <stddef.h>
#include <stdint.h>
+#include <stdbool.h>
#include <assert.h>
#include <inttypes.h>
#include "inteltool.h"
@@ -26,7 +27,7 @@
#define PCR_PORT_SIZE (64 * KiB)
struct gpio_group {
- const char *display;
+ const char *display, *name;
size_t pad_count;
size_t func_count;
const char *const *pad_names; /* indexed by 'pad * func_count + func' */
@@ -68,6 +69,7 @@
static const struct gpio_group sunrise_group_a = {
.display = "------- GPIO Group GPP_A -------",
+ .name = "gpp_a",
.pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_a_names,
@@ -102,6 +104,7 @@
static const struct gpio_group sunrise_group_b = {
.display = "------- GPIO Group GPP_B -------",
+ .name = "gpp_b",
.pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_b_names,
@@ -147,6 +150,7 @@
static const struct gpio_group sunrise_group_c = {
.display = "------- GPIO Group GPP_C -------",
+ .name = "gpp_c",
.pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_c_names,
@@ -181,6 +185,7 @@
static const struct gpio_group sunrise_group_d = {
.display = "------- GPIO Group GPP_D -------",
+ .name = "gpp_d",
.pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_d_names,
@@ -204,6 +209,7 @@
static const struct gpio_group sunrise_group_e = {
.display = "------- GPIO Group GPP_E -------",
+ .name = "gpp_e",
.pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_e_names,
@@ -238,6 +244,7 @@
static const struct gpio_group sunrise_group_f = {
.display = "------- GPIO Group GPP_F -------",
+ .name = "gpp_f",
.pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_f_names,
@@ -272,6 +279,7 @@
static const struct gpio_group sunrise_group_g = {
.display = "------- GPIO Group GPP_G -------",
+ .name = "gpp_g",
.pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_g_names,
@@ -306,6 +314,7 @@
static const struct gpio_group sunrise_group_h = {
.display = "------- GPIO Group GPP_H -------",
+ .name = "gpp_h",
.pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_h_names,
@@ -340,6 +349,7 @@
static const struct gpio_group sunrise_group_gpd = {
.display = "-------- GPIO Group GPD --------",
+ .name = "gpd",
.pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_gpd_names,
@@ -372,6 +382,7 @@
static const struct gpio_group sunrise_group_i = {
.display = "------- GPIO Group GPP_I -------",
+ .name = "gpp_i",
.pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4,
.func_count = 4,
.pad_names = sunrise_group_i_names,
@@ -393,6 +404,100 @@
&sunrise_community_gpd, &sunrise_community_i,
};
+static void print_devtree_gpio(const size_t pad,
+ const uint32_t dw0, const uint32_t dw1)
+{
+ const size_t tx_state = dw0 >> 0 & 1;
+ const size_t tx_disable = dw0 >> 8 & 1;
+ const size_t rx_disable = dw0 >> 9 & 1;
+ const size_t pad_mode = dw0 >> 10 & 7;
+ const size_t route_nmi = dw0 >> 17 & 1;
+ const size_t route_smi = dw0 >> 18 & 1;
+ const size_t route_sci = dw0 >> 19 & 1;
+ const size_t route_apic = dw0 >> 20 & 1;
+ const size_t rx_invert = dw0 >> 23 & 1;
+ const size_t rx_evcfg = dw0 >> 25 & 3;
+ const size_t rx_raw1 = dw0 >> 28 & 1;
+ const size_t rx_padsel = dw0 >> 29 & 1;
+ const size_t pad_reset = dw0 >> 30 & 3;
+ const size_t int_sel = dw1 >> 0 & 0xff;
+ const size_t term = dw1 >> 10 & 0x0f;
+
+ printf("\t\t\tgpio %2zd ", pad);
+ if (!pad_mode) {
+ if (!rx_disable) printf("in");
+ if (!tx_disable) printf("out tx%zd", tx_state);
+ printf(" ");
+ } else {
+ printf("native%zd ", pad_mode);
+ }
+
+ if (!pad_mode && !rx_disable) {
+ if (route_nmi) printf("nmi ");
+ if (route_smi) printf("smi ");
+ if (route_sci) printf("sci ");
+ if (route_apic) printf("apic ");
+ }
+ if (pad_mode || !rx_disable) {
+ if (rx_invert) printf("rxinv ");
+ }
+ if (!pad_mode && !rx_disable) {
+ switch (rx_evcfg) {
+ case 0: printf("level "); break;
+ case 1: printf("edge "); break;
+ case 2: printf("drive0 "); break;
+ default: printf("evcfg_reserved "); break;
+ }
+ }
+ if (pad_mode || !rx_disable) {
+ if (rx_raw1) printf("raw1 ");
+ }
+ if (pad_mode) {
+ if (rx_padsel) printf("intpad ");
+ }
+
+ switch (pad_reset) {
+ case 0: printf("rsmrst "); break;
+ case 1: break;
+ case 2: printf("pltrst "); break;
+ default: printf("rstcfg_reserved "); break;
+ }
+
+ if (pad_mode || !rx_disable)
+ printf("intsel:%zd ", int_sel);
+
+ switch (term) {
+ case 0: case 8: case 15: break;
+ case 2: printf("pd5k "); break;
+ case 4: printf("pd20k "); break;
+ case 9: printf("pu1k "); break;
+ case 10: printf("pu5k "); break;
+ case 11: printf("pu2k "); break;
+ case 12: printf("pu20k "); break;
+ case 13: printf("pu667 "); break;
+ default: printf("term_reserved "); break;
+ }
+
+ printf("end\n");
+}
+
+static void print_devtree_group(const uint8_t pid, size_t pad_cfg,
+ const struct gpio_group *const group)
+{
+ size_t p;
+
+ printf("\t\tgpiogroup %s\n", group->name);
+
+ for (p = 0; p < group->pad_count; ++p, pad_cfg += 8) {
+ const uint32_t dw0 = read_pcr32(pid, pad_cfg);
+ const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4);
+
+ print_devtree_gpio(p, dw0, dw1);
+ }
+
+ printf("\t\tend\n");
+}
+
static const char *decode_pad_mode(const struct gpio_group *const group,
const size_t pad, const uint32_t dw0)
{
@@ -423,13 +528,15 @@
}
}
-static void print_gpio_community(const struct gpio_community *const community)
+static void print_gpio_community(const struct gpio_community *const community,
+ const bool devtree_mode)
{
size_t group, pad_count;
size_t pad_cfg; /* offset in bytes under this communities PCR port */
- printf("%s\n\nPCR Port ID: 0x%06zx\n\n",
- community->name, (size_t)community->pcr_port_id << 16);
+ if (!devtree_mode)
+ printf("%s\n\nPCR Port ID: 0x%06zx\n\n",
+ community->name, (size_t)community->pcr_port_id << 16);
for (group = 0, pad_count = 0; group < community->group_count; ++group)
pad_count += community->groups[group]->pad_count;
@@ -442,13 +549,18 @@
}
for (group = 0; group < community->group_count; ++group) {
- print_gpio_group(community->pcr_port_id,
- pad_cfg, community->groups[group]);
+ if (devtree_mode) {
+ print_devtree_group(community->pcr_port_id,
+ pad_cfg, community->groups[group]);
+ } else {
+ print_gpio_group(community->pcr_port_id,
+ pad_cfg, community->groups[group]);
+ }
pad_cfg += community->groups[group]->pad_count * 8;
}
}
-void print_gpio_groups(struct pci_dev *const sb)
+void print_gpio_groups(struct pci_dev *const sb, const bool devtree_mode)
{
size_t community_count;
const struct gpio_community *const *communities;
@@ -463,8 +575,10 @@
return;
}
- printf("\n============= GPIOS =============\n\n");
+ if (!devtree_mode)
+ printf("\n============= GPIOS =============\n\n");
for (; community_count; --community_count)
- print_gpio_community(*communities++);
+ print_gpio_community(*communities++, devtree_mode);
}
+
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 7cd4363..2d803dd 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -18,6 +18,7 @@
#include <stdio.h>
#include <stdlib.h>
+#include <string.h>
#include <inttypes.h>
#include <getopt.h>
#include <fcntl.h>
@@ -366,6 +367,7 @@
" -A | --ambs: dump AMB registers\n"
" -x | --sgx: dump SGX status\n"
" -a | --all: dump all known (safe) registers\n"
+ " -D | --devtree: dump in devicetree format (as far as supported)\n"
"\n");
exit(1);
}
@@ -384,7 +386,7 @@
int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0;
int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0;
- int show_gpio_diffs = 0;
+ int show_gpio_diffs = 0, devtree_mode = 0;
static struct option long_options[] = {
{"version", 0, 0, 'v'},
@@ -405,10 +407,11 @@
{"gfx", 0, 0, 'f'},
{"ahci", 0, 0, 'R'},
{"sgx", 0, 0, 'x'},
+ {"devtree", 0, 0, 'D'},
{0, 0, 0, 0}
};
- while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRS:x",
+ while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRDS:x",
long_options, &option_index)) != EOF) {
switch (opt) {
case 'v':
@@ -476,6 +479,9 @@
case 'x':
dump_sgx = 1;
break;
+ case 'D':
+ devtree_mode = 1;
+ break;
case 'h':
case '?':
default:
@@ -623,65 +629,67 @@
gfx->vendor_id, gfx->device_id, gfxname);
/* Now do the deed */
+ if (!devtree_mode) {
+ if (dump_gpios) {
+ print_gpios(sb, 1, show_gpio_diffs);
+ printf("\n\n");
+ } else if (show_gpio_diffs) {
+ print_gpios(sb, 0, show_gpio_diffs);
+ printf("\n\n");
+ }
- if (dump_gpios) {
- print_gpios(sb, 1, show_gpio_diffs);
- printf("\n\n");
- } else if (show_gpio_diffs) {
- print_gpios(sb, 0, show_gpio_diffs);
- printf("\n\n");
+ if (dump_rcba) {
+ print_rcba(sb);
+ printf("\n\n");
+ }
+
+ if (dump_pmbase) {
+ print_pmbase(sb, pacc);
+ printf("\n\n");
+ }
+
+ if (dump_mchbar) {
+ print_mchbar(nb, pacc, dump_spd_file);
+ printf("\n\n");
+ }
+
+ if (dump_epbar) {
+ print_epbar(nb);
+ printf("\n\n");
+ }
+
+ if (dump_dmibar) {
+ print_dmibar(nb);
+ printf("\n\n");
+ }
+
+ if (dump_pciexbar) {
+ print_pciexbar(nb);
+ printf("\n\n");
+ }
+
+ if (dump_coremsrs) {
+ print_intel_core_msrs();
+ printf("\n\n");
+ }
+
+ if (dump_ambs)
+ print_ambs(nb, pacc);
+
+ if (dump_spi)
+ print_spi(sb);
+
+ if (dump_gfx)
+ print_gfx(gfx);
+
+ if (dump_ahci)
+ print_ahci(ahci);
+
+ if (dump_sgx)
+ print_sgx();
+ } else {
+ print_gpio_groups(sb, devtree_mode);
}
-
- if (dump_rcba) {
- print_rcba(sb);
- printf("\n\n");
- }
-
- if (dump_pmbase) {
- print_pmbase(sb, pacc);
- printf("\n\n");
- }
-
- if (dump_mchbar) {
- print_mchbar(nb, pacc, dump_spd_file);
- printf("\n\n");
- }
-
- if (dump_epbar) {
- print_epbar(nb);
- printf("\n\n");
- }
-
- if (dump_dmibar) {
- print_dmibar(nb);
- printf("\n\n");
- }
-
- if (dump_pciexbar) {
- print_pciexbar(nb);
- printf("\n\n");
- }
-
- if (dump_coremsrs) {
- print_intel_core_msrs();
- printf("\n\n");
- }
-
- if (dump_ambs)
- print_ambs(nb, pacc);
-
- if (dump_spi)
- print_spi(sb);
-
- if (dump_gfx)
- print_gfx(gfx);
-
- if (dump_ahci)
- print_ahci(ahci);
-
- if (dump_sgx)
- print_sgx();
-
/* Clean up */
pcr_cleanup();
if (ahci)
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index b8d6d0d..016199d 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -19,6 +19,7 @@
#include <commonlib/helpers.h>
+#include <stdbool.h>
#include <stdint.h>
#if defined(__GLIBC__)
@@ -302,7 +303,7 @@
int print_pmbase(struct pci_dev *sb, struct pci_access *pacc);
int print_rcba(struct pci_dev *sb);
int print_gpios(struct pci_dev *sb, int show_all, int show_diffs);
-void print_gpio_groups(struct pci_dev *sb);
+void print_gpio_groups(struct pci_dev *sb, bool devtree_mode);
int print_epbar(struct pci_dev *nb);
int print_dmibar(struct pci_dev *nb);
int print_pciexbar(struct pci_dev *nb);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3
Gerrit-Change-Number: 25509
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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