[coreboot-gerrit] Change in coreboot[master]: mainboard/google/fizz: Tune i2c parameters
Shelley Chen (Code Review)
gerrit at coreboot.org
Fri Sep 29 23:45:37 CEST 2017
Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/21773
Change subject: mainboard/google/fizz: Tune i2c parameters
......................................................................
mainboard/google/fizz: Tune i2c parameters
Tune I2C params for I2C buses 1 and 5 to ensure that the
frequency does not exceed 400KHz.
BUG=b:65058277
BRANCH=None
TEST=Measured bus frequency for audio and cr50 <= 400MHz
Change-Id: Ia82d47916958e4c199b80a845977b79c4057ac81
Signed-off-by: Shelley Chen <shchen at chromium.org>
---
M src/mainboard/google/fizz/devicetree.cb
1 file changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21773/1
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 3989ec4..3590d6e 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -220,7 +220,25 @@
# Configure I2C1 for cr50 TPM. Early init is required to set up a BAR
# for TPM communication before memory is up.
register "i2c[1]" = "{
- .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 156,
+ .scl_hcnt = 139,
+ .sda_hold = 36,
+ },
+ .early_init = 1,
+ }"
+
+ # audio
+ register "i2c[5]" = "{
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 156,
+ .scl_hcnt = 139,
+ .sda_hold = 36,
+ },
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
--
To view, visit https://review.coreboot.org/21773
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia82d47916958e4c199b80a845977b79c4057ac81
Gerrit-Change-Number: 21773
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen at google.com>
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