[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Add delay after resetting UART

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21731


Change subject: soc/amd/stoneyridge: Add delay after resetting UART
......................................................................

soc/amd/stoneyridge: Add delay after resetting UART

On warm boot, when we reset the UART, the registers are not available
immediately afterwards.  This delay allows the following uart_init
function to set up the registers correctly.  This fixes a 30 second
pause on warm boots.

Note that this delay was determined just from testing, and may not
be sufficient in all cases.  Further testing is desirable.

BUG=b:65853981
TEST=Boot to Chrome OS, run the reboot command, verify that the long
delay is gone.

Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/soc/amd/stoneyridge/early_setup.c
1 file changed, 1 insertion(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/21731/1

diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c
index 5166a7f..74490fb 100644
--- a/src/soc/amd/stoneyridge/early_setup.c
+++ b/src/soc/amd/stoneyridge/early_setup.c
@@ -48,6 +48,7 @@
 	/* reset UART */
 	write8((void *)APU_UART0_BASE + (0x2000 * CONFIG_UART_FOR_CONSOLE)
 					+ 0x88, 0x01);
+	udelay(300);
 }
 
 void sb_pci_port80(void)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676
Gerrit-Change-Number: 21731
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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