[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Disable Cpu Ratio Override
Lijian Zhao (Code Review)
gerrit at coreboot.org
Wed Sep 27 02:32:08 CEST 2017
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21712
Change subject: mainboard/intel/cannonlake_rvp: Disable Cpu Ratio Override
......................................................................
mainboard/intel/cannonlake_rvp: Disable Cpu Ratio Override
Disable CPU Ratio override as default for CannonLake RVP platform to
avoid extra soft_reset in early stage in case of mismatch.
Change-Id: I57631f00750cc793da70b8cce85aaad0df136ebe
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/21712/2
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 119af48..ea185aa 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -32,6 +32,8 @@
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
+ register "cpuratio" = "0"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 6e7c535..7abed0c 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -32,6 +32,8 @@
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
+ register "cpuratio" = "0"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I57631f00750cc793da70b8cce85aaad0df136ebe
Gerrit-Change-Number: 21712
Gerrit-PatchSet: 2
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: John Zhao <john.zhao at intel.com>
Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula at intel.com>
Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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