[coreboot-gerrit] Change in coreboot[master]: [HACK] arch/riscv: build the code without RVC

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21686


Change subject: [HACK] arch/riscv: build the code without RVC
......................................................................

[HACK] arch/riscv: build the code without RVC

RVC (the RISC-V Compressed extension) cases problems for
handle_misaligned_{load,store}, but I feel there should be a better
solution than simply hard-coding the architecture variant that I'm
currently testing against.

IOW: Do not merge, for now.

Change-Id: Iea8fc6657c196f8580a51f0cb75d5532254bd7c2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/arch/riscv/Makefile.inc
1 file changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/21686/1

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index c68fd1e..47dbe7a 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -15,9 +15,9 @@
 ##
 ################################################################################
 
-riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany
+riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=rv64imafd
 
-riscv_asm_flags =
+riscv_asm_flags = -march=rv64imafd
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 check-ramstage-overlap-regions += stack

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iea8fc6657c196f8580a51f0cb75d5532254bd7c2
Gerrit-Change-Number: 21686
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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