[coreboot-gerrit] Change in coreboot[master]: soc/intel: lpc: Use IS_POWER_OF_2 instead of open-coding it
Jonathan Neuschäfer (Code Review)
gerrit at coreboot.org
Sat Sep 23 22:31:56 CEST 2017
Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21655
Change subject: soc/intel: lpc: Use IS_POWER_OF_2 instead of open-coding it
......................................................................
soc/intel: lpc: Use IS_POWER_OF_2 instead of open-coding it
Change-Id: I7a10a3fa5e1e9140a558f61109d0c9094d46e521
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/soc/intel/common/block/lpc/lpc_lib.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/21655/1
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 6b5f29a..c4144cb 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -161,7 +161,7 @@
device_t dev = PCH_DEV_LPC;
uint8_t bc_cntl;
- assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
+ assert(IS_POWER_OF_2(bios_cntl_bit));
bc_cntl = pci_read_config8(dev, LPC_BIOS_CNTL);
bc_cntl |= bios_cntl_bit;
pci_write_config8(dev, LPC_BIOS_CNTL, bc_cntl);
--
To view, visit https://review.coreboot.org/21655
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7a10a3fa5e1e9140a558f61109d0c9094d46e521
Gerrit-Change-Number: 21655
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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