[coreboot-gerrit] Change in coreboot[master]: [wip]soc/intel/cannonlake: Fill the SMI usage
Lijian Zhao (Code Review)
gerrit at coreboot.org
Sat Sep 23 02:18:28 CEST 2017
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21543
Change subject: [wip]soc/intel/cannonlake: Fill the SMI usage
......................................................................
[wip]soc/intel/cannonlake: Fill the SMI usage
Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/include/soc/msr.h
A src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/smihandler.c
A src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/common/block/include/intelblocks/smihandler.h
M src/soc/intel/common/block/smm/smitraphandler.c
10 files changed, 496 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/21543/12
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index fe80a20..bf47270 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -21,6 +21,7 @@
select HAVE_HARD_RESET
select HAVE_INTEL_FIRMWARE
select HAVE_MONOTONIC_TIMER
+ select HAVE_SMI_HANDLER
select INTEL_CAR_NEM_ENHANCED
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
@@ -28,7 +29,9 @@
select POSTCAR_CONSOLE
select POSTCAR_STAGE
select REG_SCRIPT
+ select RELOCATABLE_MODULES
select RELOCATABLE_RAMSTAGE
+ select SMM_TSEG
select SMP
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
@@ -53,6 +56,7 @@
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
select SOC_INTEL_COMMON_RESET
+ select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 0493c1b..1797845 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -5,6 +5,7 @@
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
+subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
@@ -34,12 +35,20 @@
ramstage-y += memmap.c
ramstage-y += pmutil.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
+ramstage-y += smmrelocate.c
ramstage-y += spi.c
ramstage-y += systemagent.c
ramstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c
ramstage-y += vr_config.c
+smm-y += gpio.c
+smm-y += pmutil.c
+smm-y += smihandler.c
+smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
+smm-$(CONFIG_UART_DEBUG) += uart.c
+smm-$(CONFIG_UART_DEBUG) += uart_pch.c
+
postcar-y += memmap.c
postcar-y += pmutil.c
postcar-y += spi.c
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 4e06577..23ffe8f 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -21,10 +21,12 @@
#include <cpu/intel/turbo.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
+#include <intelblocks/smm.h>
#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
+#include <soc/smm.h>
static void soc_fsp_load(void)
{
@@ -197,13 +199,29 @@
/* Enable Turbo */
enable_turbo();
+}
+static void per_cpu_smm_trigger(void)
+{
+ /* Relocate the SMM handler. */
+ smm_relocate();
}
static void post_mp_init(void)
{
/* Set Max Ratio */
cpu_set_max_ratio();
+
+ /*
+ * Now that all APs have been relocated as well as the BSP let SMIs
+ * start flowing.
+ */
+ smm_southbridge_enable();
+
+ /* Lock down the SMRAM space. */
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ smm_lock();
+#endif
}
static const struct mp_ops mp_ops = {
@@ -214,7 +232,11 @@
*/
.pre_mp_init = soc_fsp_load,
.get_cpu_count = get_cpu_count,
+ .get_smm_info = smm_info,
.get_microcode_info = get_microcode_info,
+ .pre_mp_smm_init = smm_initialize,
+ .per_cpu_smm_trigger = per_cpu_smm_trigger,
+ .relocation_handler = smm_relocation_handler,
.post_mp_init = post_mp_init,
};
diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h
index 931281a..6617d7f 100644
--- a/src/soc/intel/cannonlake/include/soc/msr.h
+++ b/src/soc/intel/cannonlake/include/soc/msr.h
@@ -20,22 +20,13 @@
#include <intelblocks/msr.h>
#define MSR_PIC_MSG_CONTROL 0x2e
-#define MSR_BIOS_UPGD_TRIG 0x7a
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
-#define PRMRR_PHYS_BASE_MSR 0x1f4
-#define IA32_PLATFORM_DCA_CAP 0x1f8
-#define MSR_LT_LOCK_MEMORY 0x2e7
-#define MSR_SGX_OWNEREPOCH0 0x300
-#define MSR_SGX_OWNEREPOCH1 0x301
-#define MSR_VR_CURRENT_CONFIG 0x601
-#define MSR_VR_MISC_CONFIG 0x603
+#define IA32_PLATFORM_DCA_CAP 0x1f9
#define MSR_VR_MISC_CONFIG2 0x636
-#define MSR_PP0_POWER_LIMIT 0x638
-#define MSR_PP1_POWER_LIMIT 0x640
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h
new file mode 100644
index 0000000..9121ac3
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/smm.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_SMM_H_
+#define _SOC_SMM_H_
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <fsp/memmap.h>
+#include <soc/gpio.h>
+
+struct ied_header {
+ char signature[10];
+ u32 size;
+ u8 reserved[34];
+} __packed;
+
+struct smm_relocation_params {
+ u32 smram_base;
+ u32 smram_size;
+ u32 ied_base;
+ u32 ied_size;
+ msr_t smrr_base;
+ msr_t smrr_mask;
+ msr_t emrr_base;
+ msr_t emrr_mask;
+ msr_t uncore_emrr_base;
+ msr_t uncore_emrr_mask;
+ /*
+ * The smm_save_state_in_msrs field indicates if SMM save state
+ * locations live in MSRs. This indicates to the CPUs how to adjust
+ * the SMMBASE and IEDBASE
+ */
+ int smm_save_state_in_msrs;
+};
+
+/* Mainboard handler for eSPI SMIs */
+void mainboard_smi_espi_handler(void);
+
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+ uintptr_t staggered_smbase);
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+ size_t *smm_save_state_size);
+void smm_initialize(void);
+void smm_relocate(void);
+
+#else /* CONFIG_HAVE_SMI_HANDLER */
+static inline void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+ uintptr_t staggered_smbase) {}
+static inline void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+ size_t *smm_save_state_size) {}
+static inline void smm_initialize(void) {}
+
+static inline void smm_relocate(void) {}
+#endif /* CONFIG_HAVE_SMI_HANDLER */
+
+#endif
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 29f25f2..0259cda 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -23,9 +23,64 @@
#include <intelblocks/systemagent.h>
#include <soc/bootblock.h>
#include <soc/pci_devs.h>
+#include <soc/smm.h>
#include <soc/systemagent.h>
#include <stdlib.h>
+void smm_region(void **start, size_t *size)
+{
+ *start = (void *)sa_get_tseg_base();
+ *size = sa_get_tseg_size();
+}
+
+/*
+ * Subregions within SMM
+ * +-------------------------+ BGSM
+ * | IED | IED_REGION_SIZE
+ * +-------------------------+
+ * | External Stage Cache | SMM_RESERVED_SIZE
+ * +-------------------------+
+ * | code and data |
+ * | (TSEG) |
+ * +-------------------------+ TSEG
+ */
+int smm_subregion(int sub, void **start, size_t *size)
+{
+ uintptr_t sub_base;
+ size_t sub_size;
+ void *smm_base;
+ const size_t ied_size = CONFIG_IED_REGION_SIZE;
+ const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
+
+ smm_region(&smm_base, &sub_size);
+ sub_base = (uintptr_t)smm_base;
+
+ switch (sub) {
+ case SMM_SUBREGION_HANDLER:
+ /* Handler starts at the base of TSEG. */
+ sub_size -= ied_size;
+ sub_size -= cache_size;
+ break;
+ case SMM_SUBREGION_CACHE:
+ /* External cache is in the middle of TSEG. */
+ sub_base += sub_size - (ied_size + cache_size);
+ sub_size = cache_size;
+ break;
+ case SMM_SUBREGION_CHIPSET:
+ /* IED is at the top. */
+ sub_base += sub_size - ied_size;
+ sub_size = ied_size;
+ break;
+ default:
+ return -1;
+ }
+
+ *start = (void *)sub_base;
+ *size = sub_size;
+
+ return 0;
+}
+
static void *top_of_ram_register(void)
{
int num;
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index eb3c5e3..0653e9f 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -16,8 +16,14 @@
*/
#include <intelblocks/smihandler.h>
+#include <soc/pm.h>
-static smi_handler_t southbridge_smi[SMI_STS_BITS] = {
+const struct smm_save_state_ops *get_smm_save_state_ops(void)
+{
+ return &em64t101_smm_ops;
+}
+
+const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
[APM_STS_BIT] = smihandler_southbridge_apmc,
[PM1_STS_BIT] = smihandler_southbridge_pm1,
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
new file mode 100644
index 0000000..d5d5b8e
--- /dev/null
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -0,0 +1,310 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mp.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
+#include <console/console.h>
+#include <intelblocks/smm.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/smm.h>
+#include <soc/systemagent.h>
+#include "chip.h"
+
+/* This gets filled in and used during relocation. */
+static struct smm_relocation_params smm_reloc_params;
+
+static inline void write_smrr(struct smm_relocation_params *relo_params)
+{
+ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
+ relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
+ wrmsr(SMRR_PHYS_BASE, relo_params->smrr_base);
+ wrmsr(SMRR_PHYS_MASK, relo_params->smrr_mask);
+}
+
+static void update_save_state(int cpu, uintptr_t curr_smbase,
+ uintptr_t staggered_smbase,
+ struct smm_relocation_params *relo_params)
+{
+ u32 smbase;
+ u32 iedbase;
+
+ /*
+ * The relocated handler runs with all CPUs concurrently. Therefore
+ * stagger the entry points adjusting SMBASE downwards by save state
+ * size * CPU num.
+ */
+ smbase = staggered_smbase;
+ iedbase = relo_params->ied_base;
+
+ printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
+ smbase, iedbase);
+
+ /*
+ * All threads need to set IEDBASE and SMBASE to the relocated
+ * handler region. However, the save state location depends on the
+ * smm_save_state_in_msrs field in the relocation parameters. If
+ * smm_save_state_in_msrs is non-zero then the CPUs are relocating
+ * the SMM handler in parallel, and each CPUs save state area is
+ * located in their respective MSR space. If smm_save_state_in_msrs
+ * is zero then the SMM relocation is happening serially so the
+ * save state is at the same default location for all CPUs.
+ */
+ if (relo_params->smm_save_state_in_msrs) {
+ msr_t smbase_msr;
+ msr_t iedbase_msr;
+
+ smbase_msr.lo = smbase;
+ smbase_msr.hi = 0;
+
+ /*
+ * According the BWG the IEDBASE MSR is in bits 63:32. It's
+ * not clear why it differs from the SMBASE MSR.
+ */
+ iedbase_msr.lo = 0;
+ iedbase_msr.hi = iedbase;
+
+ wrmsr(SMBASE_MSR, smbase_msr);
+ wrmsr(IEDBASE_MSR, iedbase_msr);
+ } else {
+ em64t101_smm_state_save_area_t *save_state;
+
+ save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
+ sizeof(*save_state));
+
+ save_state->smbase = smbase;
+ save_state->iedbase = iedbase;
+ }
+}
+
+/* Returns 1 if SMM MSR save state was set. */
+static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
+{
+ msr_t smm_mca_cap;
+
+ smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);
+ if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {
+ msr_t smm_feature_control;
+
+ smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
+ smm_feature_control.hi = 0;
+ smm_feature_control.lo |= SMM_CPU_SAVE_EN;
+ wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
+ relo_params->smm_save_state_in_msrs = 1;
+ }
+ return relo_params->smm_save_state_in_msrs;
+}
+
+/*
+ * The relocation work is actually performed in SMM context, but the code
+ * resides in the ramstage module. This occurs by trampolining from the default
+ * SMRAM entry point to here.
+ */
+void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
+ uintptr_t staggered_smbase)
+{
+ msr_t mtrr_cap;
+ struct smm_relocation_params *relo_params = &smm_reloc_params;
+
+ printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
+
+ /*
+ * Determine if the processor supports saving state in MSRs. If so,
+ * enable it before the non-BSPs run so that SMM relocation can occur
+ * in parallel in the non-BSP CPUs.
+ */
+ if (cpu == 0) {
+ /*
+ * If smm_save_state_in_msrs is 1 then that means this is the
+ * 2nd time through the relocation handler for the BSP.
+ * Parallel SMM handler relocation is taking place. However,
+ * it is desired to access other CPUs save state in the real
+ * SMM handler. Therefore, disable the SMM save state in MSRs
+ * feature.
+ */
+ if (relo_params->smm_save_state_in_msrs) {
+ msr_t smm_feature_control;
+
+ smm_feature_control = rdmsr(SMM_FEATURE_CONTROL_MSR);
+ smm_feature_control.lo &= ~SMM_CPU_SAVE_EN;
+ wrmsr(SMM_FEATURE_CONTROL_MSR, smm_feature_control);
+ } else if (bsp_setup_msr_save_state(relo_params))
+ /*
+ * Just return from relocation handler if MSR save
+ * state is enabled. In that case the BSP will come
+ * back into the relocation handler to setup the new
+ * SMBASE as well disabling SMM save state in MSRs.
+ */
+ return;
+ }
+
+ /* Make appropriate changes to the save state map. */
+ update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
+
+ /* Write EMRR and SMRR MSRs based on indicated support. */
+ mtrr_cap = rdmsr(MTRR_CAP_MSR);
+ if (mtrr_cap.lo & SMRR_SUPPORTED)
+ write_smrr(relo_params);
+}
+
+static void fill_in_relocation_params(device_t dev,
+ struct smm_relocation_params *params)
+{
+ void *handler_base;
+ size_t handler_size;
+ void *ied_base;
+ size_t ied_size;
+ void *tseg_base;
+ size_t tseg_size;
+ u32 emrr_base;
+ u32 emrr_size;
+ int phys_bits;
+ /* All range registers are aligned to 4KiB */
+ const u32 rmask = ~((1 << 12) - 1);
+
+ /*
+ * Some of the range registers are dependent on the number of physical
+ * address bits supported.
+ */
+ phys_bits = cpuid_eax(0x80000008) & 0xff;
+
+ smm_region(&tseg_base, &tseg_size);
+ smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
+ smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
+
+ params->smram_size = handler_size;
+ params->smram_base = (uintptr_t)handler_base;
+
+ params->ied_base = (uintptr_t)ied_base;
+ params->ied_size = ied_size;
+
+ /* SMRR has 32-bits of valid address aligned to 4KiB. */
+ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+ params->smrr_base.hi = 0;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
+ | MTRR_PHYS_MASK_VALID;
+ params->smrr_mask.hi = 0;
+
+ /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
+ emrr_base = (params->ied_base + (2 << 20)) & rmask;
+ emrr_size = params->ied_size - (2 << 20);
+
+ /*
+ * EMRR has 46 bits of valid address aligned to 4KiB. It's dependent
+ * on the number of physical address bits supported.
+ */
+ params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
+ params->emrr_base.hi = 0;
+ params->emrr_mask.lo = (~(emrr_size - 1) & rmask)
+ | MTRR_PHYS_MASK_VALID;
+ params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
+
+ /* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */
+ params->uncore_emrr_base.lo = emrr_base;
+ params->uncore_emrr_base.hi = 0;
+ params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
+ MTRR_PHYS_MASK_VALID;
+ params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
+}
+
+static void setup_ied_area(struct smm_relocation_params *params)
+{
+ char *ied_base;
+
+ struct ied_header ied = {
+ .signature = "INTEL RSVD",
+ .size = params->ied_size,
+ .reserved = {0},
+ };
+
+ ied_base = (void *)params->ied_base;
+
+ printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
+ printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
+
+ /* Place IED header at IEDBASE. */
+ memcpy(ied_base, &ied, sizeof(ied));
+
+ /* Zero out 32KiB at IEDBASE + 1MiB */
+ memset(ied_base + (1 << 20), 0, (32 << 10));
+}
+
+void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+ size_t *smm_save_state_size)
+{
+ device_t dev = SA_DEV_ROOT;
+
+ printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
+
+ fill_in_relocation_params(dev, &smm_reloc_params);
+
+ if (smm_reloc_params.ied_size)
+ setup_ied_area(&smm_reloc_params);
+
+ *perm_smbase = smm_reloc_params.smram_base;
+ *perm_smsize = smm_reloc_params.smram_size;
+ *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
+}
+
+void smm_initialize(void)
+{
+ /* Clear the SMM state in the southbridge. */
+ smm_southbridge_clear_state();
+
+ /*
+ * Run the relocation handler for on the BSP to check and set up
+ * parallel SMM relocation.
+ */
+ smm_initiate_relocation();
+
+ if (smm_reloc_params.smm_save_state_in_msrs)
+ printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
+}
+
+void smm_relocate(void)
+{
+ /*
+ * If smm_save_state_in_msrs is non-zero then parallel SMM relocation
+ * shall take place. Run the relocation handler a second time on the
+ * BSP to do * the final move. For APs, a relocation handler always
+ * needs to be run.
+ */
+ if (smm_reloc_params.smm_save_state_in_msrs)
+ smm_initiate_relocation_parallel();
+ else if (!boot_cpu())
+ smm_initiate_relocation();
+}
+
+void smm_lock(void)
+{
+ /*
+ * LOCK the SMM memory window and enable normal SMM.
+ * After running this function, only a full reset can
+ * make the SMM registers writable again.
+ */
+ printk(BIOS_DEBUG, "Locking SMM.\n");
+ pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index 389d241..5df5552 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -94,6 +94,21 @@
/*
* This function should be implemented in SOC specific code to handle
+ * MC event. The default functionality is provided in
+ * soc/intel/common/block/smm/smihandler.c
+ */
+void smihandler_southbridge_mc(
+ const struct smm_save_state_ops *save_state_ops);
+
+/*
+ * This function should be implemented in SOC specific code to handle
+ * minitor event. The default functionality is provided in
+ * soc/intel/common/block/smm/smihandler.c
+ */
+void smihandler_southbridge_monitor(
+ const struct smm_save_state_ops *save_state_ops);
+/*
+ * This function should be implemented in SOC specific code to handle
* SMI_TCO event. The default functionality is provided in
* soc/intel/common/block/smm/smihandler.c
*/
diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c
index 4a51cde..bfa9846 100644
--- a/src/soc/intel/common/block/smm/smitraphandler.c
+++ b/src/soc/intel/common/block/smm/smitraphandler.c
@@ -75,6 +75,8 @@
u32 data, mask = 0;
u8 trap_sts;
int i;
+ global_nvs_t *gnvs = smm_get_gnvs();
+
/* TRSR - Trap Status Register */
trap_sts = pcr_read8(PID_PSTH, PCR_PSTH_TRPST);
/* Clear trap(s) in TRSR */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Gerrit-Change-Number: 21543
Gerrit-PatchSet: 12
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: AndreX Andraos <andrex.andraos at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein at intel.com>
Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula at intel.com>
Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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