[coreboot-gerrit] Change in coreboot[master]: google/kahlee: Fix GPIO ASL

[Marc Jones (Code Review)]

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/21614


Change subject: google/kahlee: Fix GPIO ASL
......................................................................

google/kahlee: Fix GPIO ASL

Use a single define and set the CROS GPIO ASL device to match the
StoneyRidge GPIO HID. Pass the GPIO number and not the memory mapped address
of the GPIO. Also, add a DDN field in the GPIO ASL.

BUG=b:65597554
BRANCH=none
TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030.

Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/google/kahlee/acpi/carrizo_fch.asl
M src/mainboard/google/kahlee/chromeos.c
M src/soc/amd/stoneyridge/include/soc/gpio.h
3 files changed, 15 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/21614/1

diff --git a/src/mainboard/google/kahlee/acpi/carrizo_fch.asl b/src/mainboard/google/kahlee/acpi/carrizo_fch.asl
index 04f563e..9bf7dec 100644
--- a/src/mainboard/google/kahlee/acpi/carrizo_fch.asl
+++ b/src/mainboard/google/kahlee/acpi/carrizo_fch.asl
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include <soc/gpio.h>
+
 Device (AAHB)
 {
 	Name (_HID, "AAHB0000")
@@ -30,9 +32,10 @@
 
 Device (GPIO)
 {
-	Name (_HID, "AMD0030")
-	Name (_CID, "AMD0030")
-	Name(_UID, 0)
+	Name (_HID, GPIO_DEVICE_NAME)
+	Name (_CID, GPIO_DEVICE_NAME)
+	Name (_UID, 0)
+	Name (_DDN, GPIO_DEVICE_DESC)
 
 	Name (_CRS, ResourceTemplate()
 	{
diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c
index 156614b..ef471be 100644
--- a/src/mainboard/google/kahlee/chromeos.c
+++ b/src/mainboard/google/kahlee/chromeos.c
@@ -21,7 +21,8 @@
 #include <gpio.h>
 
 /* SPI Write protect */
-#define CROS_WP_GPIO	GPIO_122
+#define CROS_WP_GPIO		GPIO_122
+#define CROS_WP_GPIO_NUMBER	122
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
@@ -40,8 +41,8 @@
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-	CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(CROS_WP_GPIO_NUMBER, GPIO_DEVICE_NAME),
 };
 
 void mainboard_chromeos_acpi_generate(void)
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index c5b7c8a..5aa6248 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -16,10 +16,12 @@
 #ifndef __STONEYRIDGE_GPIO_H__
 #define __STONEYRIDGE_GPIO_H__
 
+#define GPIO_DEVICE_NAME	"AMD0030"
+#define GPIO_DEVICE_DESC	"GPIO Controller"
+
+#ifndef __ACPI__
 #include <soc/amd/common/amd_defs.h>
 #include <types.h>
-
-#define CROS_GPIO_DEVICE_NAME	"AmdKern"
 
 #define GPIO_PIN_STS		(1 << 16)
 #define GPIO_PULLUP_ENABLE	(1 << 20)
@@ -128,5 +130,5 @@
 #define   GPIO_148	(GPIO_BANK2_CONTROL + 0x50)
 
 typedef uint32_t gpio_t;
-
+#endif /* __ACPI__ */
 #endif /* __STONEYRIDGE_GPIO_H__ */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Gerrit-Change-Number: 21614
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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