[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Make UMA memory cacheable

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21606


Change subject: amd/stoneyridge: Make UMA memory cacheable
......................................................................

amd/stoneyridge: Make UMA memory cacheable

Use reserved_ram_resource to help ensure the UMA memory is typed
as WB.

BUG=b:65856868

Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/northbridge.c
1 file changed, 8 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/21606/1

diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 0a740cb..ec48a47 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -490,7 +490,14 @@
 				" limitk=%08llx\n", mmio_basek, basek, limitk);
 	}
 
-	add_uma_resource_below_tolm(dev, 7);
+	/* UMA is not set up yet, but infer the base & size to make cacheable */
+	uint32_t uma_base = restore_top_of_low_cacheable();
+	if (uma_base != bsp_topmem()) {
+		uint32_t uma_size = bsp_topmem() - uma_base;
+		printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
+				__func__, uma_size, uma_base);
+		reserved_ram_resource(dev, 7, uma_base / KiB, uma_size / KiB);
+	}
 
 	for (link = dev->link_list ; link ; link = link->next)
 		if (link->children)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd
Gerrit-Change-Number: 21606
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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