[coreboot-gerrit] Change in coreboot[master]: nb/intel/i945: Clear timeout bits after disabling watchdog

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21471


Change subject: nb/intel/i945: Clear timeout bits after disabling watchdog
......................................................................

nb/intel/i945: Clear timeout bits after disabling watchdog

Even with the watchdog disabled, these bits influence other hardware
blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet
before they started).

Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a
Signed-off-by: Nico Huber <nico.h at gmx.de>
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 2 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21471/1

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 1d473d3..f25d13b 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -170,6 +170,8 @@
 	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
 	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
 	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
+	outw((1 <<  3), DEFAULT_PMBASE | 0x60 | 0x04);	/* clear timeout */
+	outw((1 <<  1), DEFAULT_PMBASE | 0x60 | 0x06);	/* clear second timeout */
 	printk(BIOS_DEBUG, " done.\n");
 
 	/* Enable upper 128bytes of CMOS */

-- 
To view, visit https://review.coreboot.org/21471
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a
Gerrit-Change-Number: 21471
Gerrit-PatchSet: 1
Gerrit-Owner: Nico Huber <nico.h at gmx.de>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20170909/69f0985d/attachment.html>