[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21459


Change subject: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden
......................................................................

mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden

If LPSS UART port had been set up to hidden mode, FSP will not force
8 bit transition mode (AKA 16550 compatible UART mode).

BRANCH=none
TEST=Boot up coreboot and check LPSS UART debug printing after silicon
init. If mismatch, the print will became much slower.

Change-Id: I80619394d8f462a799c57bf0e7589dc34fe67716
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
2 files changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/21459/1

diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index a3c4c80..31a762a 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -8,6 +8,9 @@
 	register "SaGv" = "3"
 	register "FspSkipMpInit" = "1"
 	register "SmbusEnable" = "1"
+	register "SerialIoDevMode" = "{ \
+		[PchSerialIoIndexUART2] = PchSerialIoHidden, \
+	}"
 
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index a3c4c80..31a762a 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -8,6 +8,9 @@
 	register "SaGv" = "3"
 	register "FspSkipMpInit" = "1"
 	register "SmbusEnable" = "1"
+	register "SerialIoDevMode" = "{ \
+		[PchSerialIoIndexUART2] = PchSerialIoHidden, \
+	}"
 
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I80619394d8f462a799c57bf0e7589dc34fe67716
Gerrit-Change-Number: 21459
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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