[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy: enable AER for PCIe root port 0

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/21425


Change subject: mb/google/poppy: enable AER for PCIe root port 0
......................................................................

mb/google/poppy: enable AER for PCIe root port 0

Enable PCIe Advanced Error Reporting for PCIe root port 0.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/21425/1

diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 6aba677..eba72ab 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -152,6 +152,8 @@
 	register "PcieRpClkReqSupport[0]" = "1"
 	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
+	# RP 1, Enable Advanced Error Reporting
+	register PcieRpAdvancedErrorReporting[0] = "1"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce
Gerrit-Change-Number: 21425
Gerrit-PatchSet: 1
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
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