[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl1: Disable internal UARTs

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/21406


Change subject: siemens/mc_apl1: Disable internal UARTs
......................................................................

siemens/mc_apl1: Disable internal UARTs

APL internal UARTs are not used on this mainboard.

Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/mainboard/siemens/mc_apl1/devicetree.cb
1 file changed, 4 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/21406/1

diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb
index ab143f7..7f4983e 100644
--- a/src/mainboard/siemens/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/devicetree.cb
@@ -84,10 +84,10 @@
 		device pci 17.1 off end	# - I2C 5
 		device pci 17.2 off end	# - I2C 6
 		device pci 17.3 on  end	# - I2C 7
-		device pci 18.0 on  end	# - UART 0
-		device pci 18.1 on  end	# - UART 1
-		device pci 18.2 on  end	# - UART 2
-		device pci 18.3 on  end	# - UART 3
+		device pci 18.0 off end	# - UART 0
+		device pci 18.1 off end	# - UART 1
+		device pci 18.2 off end	# - UART 2
+		device pci 18.3 off end	# - UART 3
 		device pci 19.0 off end	# - SPI 0
 		device pci 19.1 off end	# - SPI 1
 		device pci 19.2 off end	# - SPI 2

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86
Gerrit-Change-Number: 21406
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
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