[coreboot-gerrit] Change in coreboot[master]: [WIP] mainboard/google/soraka: USB 2.0 tuning for port4

[Wisley Chen (Code Review)]

Wisley Chen has uploaded this change for review. ( https://review.coreboot.org/21403


Change subject: [WIP] mainboard/google/soraka: USB 2.0 tuning for port4
......................................................................

[WIP] mainboard/google/soraka: USB 2.0 tuning for port4

Fine tune usb 2.0 strength for port 4 to pass eye diagram.

BUG=b:65306272
TEST=build on soraka, measure usb2.0 eye diagram, and result is pass.

Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb
Signed-off-by: Wisley Chen <wisley.chen at quantatw.com>
---
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/21403/1

diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index b39092b..fea3372 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -156,7 +156,7 @@
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
+	register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)"		# Type-C Port 2
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
 	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port
 

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb
Gerrit-Change-Number: 21403
Gerrit-PatchSet: 1
Gerrit-Owner: Wisley Chen <wisley.chen at quantatw.com>
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