[coreboot-gerrit] Change in coreboot[master]: cpu/intel/slot_1: Increase CAR size

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21349


Change subject: cpu/intel/slot_1: Increase CAR size
......................................................................

cpu/intel/slot_1: Increase CAR size

Increase DCACHE_RAM_SIZE to 8KiB from 4KiB and adjust DCACHE_RAM_BASE
to match.

Boot tested on asus/p2b-ls using a 1400MHz Tualeron.

Change-Id: I5b440e7be4f3149378db88872872012c92049c20
Signed-off-by: Keith Hui <buurin at gmail.com>
---
M src/cpu/intel/slot_1/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/21349/1

diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index a98232e..f535a03 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -28,10 +28,10 @@
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xcf000
+	default 0xce000
 
 config DCACHE_RAM_SIZE
 	hex
-	default 0x01000
+	default 0x02000
 
 endif

-- 
To view, visit https://review.coreboot.org/21349
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5b440e7be4f3149378db88872872012c92049c20
Gerrit-Change-Number: 21349
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin at gmail.com>
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