[coreboot-gerrit] Change in coreboot[master]: cpu/intel/car/cache_as_ram.inc: Simplify code path
Keith Hui (Code Review)
gerrit at coreboot.org
Fri Sep 1 23:59:24 CEST 2017
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21329
Change subject: cpu/intel/car/cache_as_ram.inc: Simplify code path
......................................................................
cpu/intel/car/cache_as_ram.inc: Simplify code path
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE and
CONFIG_DCACHE_RAM_SIZE for consistency. This fixes a bug that prevents
migrating cpu/intel/slot_1 & nb/intel/i440bx to EARLY_CBMEM_INIT.
Exclude a Hyperthreading-specific code path when building for
slot_1 or pga370, which predates HT.
Do not clear MTRRs that will be programmed immediately afterwards.
Remove a block of CAR testing code currently blocked out by #if.
Newer CAR code don't even do it anymore.
Do not set %ebp before calling romstage_main(). We know it's not
needed.
The check for CONFIG_DCACHE_RAM_SIZE < 0x1000 is not needed;
checking that it is multiples of 4k will catch it.
Clarify the purpose of various code in the file.
Boot tested on ASUS P2B-LS mainboard.
Brought to you by https://review.coreboot.org/c/20977/.
Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7
Signed-off-by: Keith Hui <buurin at gmail.com>
---
M src/cpu/intel/car/cache_as_ram.inc
1 file changed, 31 insertions(+), 73 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/21329/1
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index ac17571..ee1d577 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -22,13 +22,15 @@
#include <cpu/x86/lapic_def.h>
#include <cpu/x86/post_code.h>
-#define CacheSize CONFIG_DCACHE_RAM_SIZE
-#define CacheBase (0xd0000 - CacheSize)
-
/* Save the BIST result. */
movl %eax, %ebp
CacheAsRam:
+/*
+ * Only SLOT_1, SOCKET_(FC_)PGA370 and SOCKET_MPGA479M use this code and HT
+ * was only introduced for 479. Include this HT-specific code only on 479.
+ */
+#if IS_ENABLED(CONFIG_CPU_INTEL_SOCKET_MPGA479M)
/* Check whether the processor has HT capability. */
movl $01, %eax
cpuid
@@ -104,6 +106,7 @@
jz LogicalAP_SIPINotdone
NotHtProcessor:
+#endif
/* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRR_DEF_TYPE_MSR, %ecx
xorl %edx, %edx
@@ -130,8 +133,13 @@
.long MTRR_FIX_64K_00000
.long MTRR_FIX_16K_80000
.long MTRR_FIX_16K_A0000
+ /* C0000 will be set later if DCACHE_RAM_BASE is set below 0xc8000.
+ * Don't try to set it twice.
+ */
+#if CONFIG_DCACHE_RAM_BASE >= 0xc8000
.long MTRR_FIX_4K_C0000
- .long MTRR_FIX_4K_C8000
+#endif
+ /* C8000 will be set later. */
.long MTRR_FIX_4K_D0000
.long MTRR_FIX_4K_D8000
.long MTRR_FIX_4K_E0000
@@ -142,8 +150,7 @@
/* var MTRR MSRs */
.long MTRR_PHYS_BASE(0)
.long MTRR_PHYS_MASK(0)
- .long MTRR_PHYS_BASE(1)
- .long MTRR_PHYS_MASK(1)
+ /* var MTRR #1 will be set next for XIP ROM. Don't try to set it twice. */
.long MTRR_PHYS_BASE(2)
.long MTRR_PHYS_MASK(2)
.long MTRR_PHYS_BASE(3)
@@ -203,32 +210,27 @@
*/
.endm
-#if CacheSize > 0x10000
+#if CONFIG_DCACHE_RAM_SIZE > 0x10000
#error Invalid CAR size, must be at most 64k.
#endif
-#if CacheSize < 0x1000
-#error Invalid CAR size, must be at least 4k. This is a processor limitation.
-#endif
-#if (CacheSize & (0x1000 - 1))
+/* This check will also catch DCACHE_RAM_SIZE < 0x1000 */
+#if (CONFIG_DCACHE_RAM_SIZE & (0x1000 - 1))
#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
#endif
-#if CacheSize > 0x8000
+#if CONFIG_DCACHE_RAM_SIZE > 0x8000
/* Enable caching for 32K-64K using fixed MTRR. */
movl $MTRR_FIX_4K_C0000, %ecx
- simplemask CacheSize, 0x8000
+ simplemask CONFIG_DCACHE_RAM_SIZE, 0x8000
wrmsr
#endif
/* Enable caching for 0-32K using fixed MTRR. */
movl $MTRR_FIX_4K_C8000, %ecx
- simplemask CacheSize, 0
+ simplemask CONFIG_DCACHE_RAM_SIZE, 0
wrmsr
- /*
- * Enable write base caching so we can do execute in place (XIP)
- * on the flash ROM.
- */
+ /* Enable cache for our code in Flash because we do XIP here. */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
/*
@@ -237,7 +239,7 @@
*/
movl $copy_and_run, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
- orl $MTRR_TYPE_WRBACK, %eax
+ orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
@@ -250,70 +252,26 @@
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
movl %eax, %cr0
- /* Read the range with lodsl. */
- movl $CacheBase, %esi
+ /* Read the CAR region. This will also fill up the cache.
+ * IMPORTANT: This step is mandatory.
+ */
+ movl $CONFIG_DCACHE_RAM_BASE, %esi
cld
- movl $(CacheSize >> 2), %ecx
+ movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
rep lodsl
- /* Clear the range. */
- movl $CacheBase, %edi
- movl $(CacheSize >> 2), %ecx
+ /* Clear the CAR region. */
+ movl $CONFIG_DCACHE_RAM_BASE, %edi
+ movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
xorl %eax, %eax
rep stosl
-#if 0
- /* Check the cache as ram. */
- movl $CacheBase, %esi
- movl $(CacheSize >> 2), %ecx
-.xin1:
- movl %esi, %eax
- movl %eax, (%esi)
- decl %ecx
- je .xout1
- add $4, %esi
- jmp .xin1
-.xout1:
-
- movl $CacheBase, %esi
- // movl $(CacheSize >> 2), %ecx
- movl $4, %ecx
-.xin1x:
- movl %esi, %eax
-
- movl $0x4000, %edx
- movb %ah, %al
-.testx1:
- outb %al, $0x80
- decl %edx
- jnz .testx1
-
- movl (%esi), %eax
- cmpb 0xff, %al
- je .xin2 /* Don't show. */
-
- movl $0x4000, %edx
-.testx2:
- outb %al, $0x80
- decl %edx
- jnz .testx2
-
-.xin2:
- decl %ecx
- je .xout1x
- add $4, %esi
- jmp .xin1x
-.xout1x:
-#endif
-
- movl $(CacheBase + CacheSize - 4), %eax
+ movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
lout:
/* Restore the BIST result. */
movl %ebp, %eax
- /* We need to set EBP? No need. */
- movl %esp, %ebp
pushl %eax /* BIST */
call romstage_main
@@ -329,7 +287,7 @@
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
- /* Clear sth. */
+ /* Clear the fixed MTRR we used. */
movl $MTRR_FIX_4K_C8000, %ecx
xorl %edx, %edx
xorl %eax, %eax
--
To view, visit https://review.coreboot.org/21329
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7
Gerrit-Change-Number: 21329
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin at gmail.com>
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