[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Add definitions for various NB registers

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22244


Change subject: amd/stoneyridge: Add definitions for various NB registers
......................................................................

amd/stoneyridge: Add definitions for various NB registers

Add #define values for the first MMIO base/limit, the first I/O
base/limit, and VGA enable registers.

Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/include/soc/northbridge.h
1 file changed, 11 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/22244/1

diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 45c67c2..9113878 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -26,9 +26,20 @@
 # define CPU_CNT_MASK		0x1f /*  CpuCnt + 1 = no. CPUs */
 
 /* D18F1 - Address Map Registers */
+#define D18F1_MMIO_BASE0_LO	0x80
+# define MMIO_WE		(1 << 1)
+# define MMIO_RE		(1 << 0)
+#define D18F1_MMIO_LIMIT0_LO	0x84
+# define MMIO_NP		(1 << 7)
+#define D18F1_IO_BASE0		0xc0
+# define IO_WE			(1 << 1)
+# define IO_RE			(1 << 0)
+#define D18F1_IO_LIMIT0		0xc4
 #define D18F1_DRAM_HOLE		0xf0
 # define DRAM_HOIST_VALID	(1 << 1)
 # define DRAM_HOLE_VALID	(1 << 0)
+#define D18F1_VGAEN		0xf4
+# define VGA_ADDR_ENABLE	(1 << 0)
 
 enum {
 	/* SMM handler area. */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760
Gerrit-Change-Number: 22244
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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