[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Turnoff XTAL Disqualification for XTAL Shutdown

[Roy Mingi Park (Code Review)]

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/22237


Change subject: soc/intel/skylake: Turnoff XTAL Disqualification for XTAL Shutdown
......................................................................

soc/intel/skylake: Turnoff XTAL Disqualification for XTAL Shutdown

24MHz Crystal Shutdown Qualification bit (0x31Ch[22]) need to be '0'
if system can enter S0ix with XTAL Shutdown.

BUG=None
BRANCH=None
TEST=Build for kabylake board with XTAL Disqualification off in pmc.h
And read 24MHz Crystal Shutdown Qualification bit (0x31Ch[22])

iotools mmio_read32 0xFE00031c should return '0' on BIT[22]

Change-Id: I8abc6e9b88b3bc25cf865824aa14b292ac0524ef
Signed-off-by: Roy Mingi Park <roy.mingi.park at intel.com>
---
M src/soc/intel/skylake/include/soc/pmc.h
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/22237/1

diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index bd86f95..76bfdd5 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -97,5 +97,5 @@
 #define GBLRST_CAUSE0		0x124
 #define GBLRST_CAUSE1		0x128
 #define CIR31C			0x31c
-#define  XTALSDQDIS		(1 << 22)
+#define  XTALSDQDIS		(0 << 22)
 #endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8abc6e9b88b3bc25cf865824aa14b292ac0524ef
Gerrit-Change-Number: 22237
Gerrit-PatchSet: 1
Gerrit-Owner: Roy Mingi Park <roy.mingi.park at intel.com>
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