[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/raminit: Add extended memtest

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/22200


Change subject: nb/intel/sandybridge/raminit: Add extended memtest
......................................................................

nb/intel/sandybridge/raminit: Add extended memtest

Run an regular or extended memtest on native raminit to make sure the DRAM
is usable. As it's very intrusive, the test is only run on cold-boot, but
not on S3 resume.

Change-Id: I31bcf8348c97b9461ee0aa792b3e53c0225d7d48
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/raminit.c
2 files changed, 22 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/22200/1

diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 1a47f0d..23ae067 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -133,6 +133,13 @@
 	  The path and filename of the file to use as System Agent
 	  binary.
 
+config RAMINIT_EXTENDED_MEMTEST
+	bool "Run extended memtest on raminit"
+	default n
+	help
+	  Run extended memtest over all usable memory below 4GiB.
+	  This will delay raminit training by several seconds.
+
 endif # !USE_NATIVE_RAMINIT
 
 endif
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index bdba748..cd6f5e5 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -445,8 +445,21 @@
 	/* Zone config */
 	dram_zones(&ctrl, 0);
 
-	/* Non intrusive, fast ram check */
-	quick_ram_check();
+	if (!s3resume) {
+		/* TODO: use PAE */
+                /* Test memory below 4GiB */
+                const size_t stepk = IS_ENABLED(CONFIG_RAMINIT_EXTENDED_MEMTEST)
+                        ? (64 << 10) : (4 << 10);
+                const u32 tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), 0xb8);
+                const size_t endk = (tseg_base & 0xfff00000) >> 10;
+
+                for (size_t basek = 0; basek < endk; basek += stepk)
+                        ram_check(basek << 10, (basek + (1 << 10)) << 10);
+
+	} else {
+		/* Non intrusive, fast ram check */
+		quick_ram_check();
+	}
 
 	intel_early_me_status();
 	intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);

-- 
To view, visit https://review.coreboot.org/22200
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I31bcf8348c97b9461ee0aa792b3e53c0225d7d48
Gerrit-Change-Number: 22200
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
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