[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: avoid double accounting for power state

[Patrick Georgi (Code Review)]

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/22179


Change subject: soc/intel/apollolake: avoid double accounting for power state
......................................................................

soc/intel/apollolake: avoid double accounting for power state

intel/common's pmclib already keeps track of the power state (since
commit f073872e22728fe8ade85022740af95cc129e9a5 and doing it twice can
mess up the data that ends up in cbmem (and from there, everything else),
so don't.

BUG=b:67976359
BRANCH=none
TEST=builds

Change-Id: I69c804a2a3bee43add940d8c827b7250f2fe9024
Signed-off-by: Patrick Georgi <pgeorgi at google.com>
---
M src/soc/intel/apollolake/romstage.c
1 file changed, 2 insertions(+), 20 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22179/1

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index cc02ff5..f315e61 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -53,8 +53,6 @@
 #include <compiler.h>
 #include "chip.h"
 
-static struct chipset_power_state power_state CAR_GLOBAL;
-
 static const uint8_t hob_variable_guid[16] = {
 	0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41,
 	0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42,
@@ -110,22 +108,6 @@
 	reg |= TCO_TMR_HLT;
 	outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
 }
-
-static void migrate_power_state(int is_recovery)
-{
-	struct chipset_power_state *ps_cbmem;
-	struct chipset_power_state *ps_car;
-
-	ps_car = car_get_var_ptr(&power_state);
-	ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem));
-
-	if (ps_cbmem == NULL) {
-		printk(BIOS_DEBUG, "Unable to add power state to cbmem!\n");
-		return;
-	}
-	memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
-}
-ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state);
 
 /*
  * Punit Initialization code. This all isn't documented, but
@@ -211,7 +193,7 @@
 	struct postcar_frame pcf;
 	uintptr_t top_of_ram;
 	bool s3wake;
-	struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+	struct chipset_power_state *ps = pmc_get_power_state();
 	void *smm_base;
 	size_t smm_size, var_size;
 	const void *new_var_data;
@@ -312,7 +294,7 @@
 	if (mupd->FspmArchUpd.BootMode != FSP_BOOT_WITH_FULL_CONFIGURATION)
 		return;
 
-	ps = car_get_var_ptr(&power_state);
+	ps = pmc_get_power_state();
 
 	if (ps->gen_pmcon1 & WARM_RESET_STS) {
 		printk(BIOS_INFO, "Full retrain unsupported on warm reboot.\n");

-- 
To view, visit https://review.coreboot.org/22179
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I69c804a2a3bee43add940d8c827b7250f2fe9024
Gerrit-Change-Number: 22179
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Georgi <pgeorgi at google.com>
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