[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801jx: Store initial timestamp in bootblock

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22100


Change subject: sb/intel/i82801jx: Store initial timestamp in bootblock
......................................................................

sb/intel/i82801jx: Store initial timestamp in bootblock

The function to fetch this timestamp is already present.

Change-Id: I760aea8a867339764be9ca627b2ccdff4fd18e30
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/i82801jx/bootblock.c
1 file changed, 13 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/22100/1

diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c
index cc685c4..b41f8a9 100644
--- a/src/southbridge/intel/i82801jx/bootblock.c
+++ b/src/southbridge/intel/i82801jx/bootblock.c
@@ -14,7 +14,19 @@
  */
 
 #include <arch/io.h>
+#include <cpu/x86/tsc.h>
 #include "i82801jx.h"
+
+static void store_initial_timestamp(void)
+{
+	/* We have two 32bit scratchpad registers available:
+	 * D0:F0  0xdc (SKPAD)
+	 * D31:F2 0xd0 (SATA SP)
+	 */
+	tsc_t tsc = rdtsc();
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
+}
 
 static void enable_spi_prefetch(void)
 {
@@ -31,6 +43,7 @@
 
 static void bootblock_southbridge_init(void)
 {
+	store_initial_timestamp();
 	enable_spi_prefetch();
 
 	/* Enable RCBA */

-- 
To view, visit https://review.coreboot.org/22100
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I760aea8a867339764be9ca627b2ccdff4fd18e30
Gerrit-Change-Number: 22100
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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