[coreboot-gerrit] Change in coreboot[master]: kahlee: Set Kahlee GPEs
Marc Jones (Code Review)
gerrit at coreboot.org
Wed Oct 18 07:17:00 CEST 2017
Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22096
Change subject: kahlee: Set Kahlee GPEs
......................................................................
kahlee: Set Kahlee GPEs
Add GPE configuration table.
Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22).
Set GPE ASL methods for:
PCIE/WLAN 8h
EHCI 18h
XHCI 1fh
BUG=b:63268311
BRANCH=none
TEST=Test lidswitch powers the device on and off at the login screen.
Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
M src/mainboard/google/kahlee/acpi/gpe.asl
M src/mainboard/google/kahlee/dsdt.asl
M src/mainboard/google/kahlee/ec.h
M src/mainboard/google/kahlee/gpio.c
M src/mainboard/google/kahlee/mainboard.c
A src/mainboard/google/kahlee/mainboard.h
6 files changed, 66 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/22096/1
diff --git a/src/mainboard/google/kahlee/acpi/gpe.asl b/src/mainboard/google/kahlee/acpi/gpe.asl
index eed4e81..6e0d547 100644
--- a/src/mainboard/google/kahlee/acpi/gpe.asl
+++ b/src/mainboard/google/kahlee/acpi/gpe.asl
@@ -15,68 +15,26 @@
Scope (\_GPE)
{
- /* General event 3 */
- Method (_L03)
- {
- /* DBGO ("\\_GPE\\_L00\n") */
- Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Legacy PM event */
+ /* PCIE WLAN Wake event */
Method (_L08)
{
/* DBGO ("\\_GPE\\_L08\n") */
- }
-
- /* Temp warning (TWarn) event */
- Method (_L09)
- {
- /* DBGO ("\\_GPE\\_L09\n") */
- /* Notify (\_TZ.TZ00, 0x80) */
- }
-
- /* USB controller PME# */
- Method (_L0B)
- {
- /* DBGO ("\\_GPE\\_L0B\n") */
- Notify (\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
- /* ExtEvent0 SCI event */
- Method (_L10)
- {
- /* DBGO ("\\_GPE\\_L10\n") */
- }
-
- /* ExtEvent1 SCI event */
- Method (_L11)
- {
- /* DBGO ("\\_GPE\\_L11\n") */
- }
-
- /* GPIO0 or GEvent8 event */
+ /* EHCI USB controller PME# SCIMAP24*/
Method (_L18)
{
- /* DBGO ("\\_GPE\\_L18\n") */
- Notify (\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ /* DBGO ("\\_GPE\\_L0B\n") */
+ Notify (\_SB.PCI0.EHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
- /* Azalia SCI event */
- Method (_L1B)
+ /* XHCI USB controller PME# SCIMAP56*/
+ Method (_L1F)
{
- /* DBGO("\\_GPE\\_L1B\n") */
- Notify (\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ /* DBGO ("\\_GPE\\_L0B\n") */
+ Notify (\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index 3f91c7a..717d4bb 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -59,8 +59,6 @@
Device(PWRB) {
Name(_HID, EISAID("PNP0C0C"))
Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04})
- Name(_STA, 0x0B)
}
Device(PCI0) {
diff --git a/src/mainboard/google/kahlee/ec.h b/src/mainboard/google/kahlee/ec.h
index deb2cb1..495ad69 100644
--- a/src/mainboard/google/kahlee/ec.h
+++ b/src/mainboard/google/kahlee/ec.h
@@ -19,8 +19,8 @@
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
-/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
-#define EC_SCI_GPI 24
+/* AGPIO22 -> GPE3 */
+#define EC_SCI_GPI 3
/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
#define EC_SMI_GPI 23
diff --git a/src/mainboard/google/kahlee/gpio.c b/src/mainboard/google/kahlee/gpio.c
index f586c35..8eadab1 100644
--- a/src/mainboard/google/kahlee/gpio.c
+++ b/src/mainboard/google/kahlee/gpio.c
@@ -15,6 +15,8 @@
#include <AGESA.h>
#include <FchPlatform.h>
+#include <mainboard.h>
+#include <soc/smi.h>
#include <soc/southbridge.h>
#include <stdlib.h>
@@ -91,3 +93,28 @@
{-1}
};
+
+/*
+ * GPE setup table must match ACPI GPE ASL
+ * { gevent, gpe, direction, level }
+ */
+static const struct sci_source_t gpe_table[] = {
+
+ /* EC AGPIO22/Gevent3 -> GPE 3 */
+ {3, 3, SMI_SCI_LVL_HIGH, SMI_SCI_LVL},
+
+ /* PCIE/WLAN AGPIO2/Gevent8 -> GPE8 */
+ {8, 8, SMI_SCI_LVL_HIGH, SMI_SCI_LVL},
+
+ /* EHCI USB_PME -> GPE24 */
+ {24, 24, SMI_SCI_LVL_HIGH, SMI_SCI_LVL},
+
+ /* XHCIC0_-> GPE31 */
+ {56, 31, SMI_SCI_LVL_HIGH, SMI_SCI_LVL},
+};
+
+const struct sci_source_t * get_gpe_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpe_table);
+ return gpe_table;
+}
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 48a05a9..01225b8 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -19,6 +19,8 @@
#include <agesawrapper.h>
#include <amd_pci_util.h>
#include <ec.h>
+#include <mainboard.h>
+#include <soc/smi.h>
#include <vendorcode/google/chromeos/chromeos.h>
/***********************************************************
@@ -79,7 +81,13 @@
static void mainboard_init(void *chip_info)
{
+ const struct sci_source_t* gpes;
+ size_t num;
+
mainboard_ec_init();
+
+ gpes = get_gpe_table(&num);
+ gpe_configure_sci(gpes, num);
}
/*************************************************
diff --git a/src/mainboard/google/kahlee/mainboard.h b/src/mainboard/google/kahlee/mainboard.h
new file mode 100644
index 0000000..ecda535
--- /dev/null
+++ b/src/mainboard/google/kahlee/mainboard.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_H
+#define MAINBOARD_H
+
+const struct sci_source_t * get_gpe_table(size_t *num);
+
+#endif /* MAINBOARD_H */
--
To view, visit https://review.coreboot.org/22096
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Gerrit-Change-Number: 22096
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20171018/d6687b4c/attachment-0001.html>
More information about the coreboot-gerrit
mailing list