[coreboot-gerrit] Change in coreboot[master]: (WIP) soc/amd/common: Add FV access to SPI
John E. Kabat Jr. (Code Review)
gerrit at coreboot.org
Tue Oct 17 03:26:00 CEST 2017
Hello frank vibrans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/22065
to review the following change.
Change subject: (WIP) soc/amd/common: Add FV access to SPI
......................................................................
(WIP) soc/amd/common: Add FV access to SPI
Add firmware volume related access to SPI code. Translates
fmap access requests to SPI flash requests.
TODO: Update this code to work for S3 save and restore.
Change-Id: I32208a214a6896308833ff34d459d5513b60ba7a
Signed-off-by: Frank Vibrans <frank.vibrans at scarletltd.com>
---
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/spi/spi.c
2 files changed, 186 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/22065/1
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index c06d097..b303450 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -58,4 +58,87 @@
/* SPI related functions called from AMD vendorcode */
void spi_SaveS3info(uint32_t pos, size_t size, uint8_t *buf, u32 len);
+/*
++ * EFI_FVB_ATTRIBUTES_2
++ * From UEFI PI spec rev. 1.6
++ *
++ * The SPI attributes are currently defined as:
++ *
++ * EFI_FVB2_READ_ENABLED_CAP | EFI_FVB2_READ_STATUS |
++ * EFI_FVB2_WRITE_ENABLED_CAP | EFI_FVB2_WRITE_STATUS |
++ * EFI_FVB2_STICKY_WRITE | EFI_FVB2_MEMORY_MAPPED | EFI_FVB2_ERASE_POLARITY |
++ * EFI_FVB2_ALIGNMENT_8M | EFI_FVB2_WEAK_ALIGNMENT
++ *
++ * All other bits are 0.
++ */
+#define SPI_FV_ATTRIBUTES 0x80170e36
+
+/* Attributes bit definitions */
+#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
+#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
+#define EFI_FVB2_READ_STATUS 0x00000004
+
+#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
+#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
+#define EFI_FVB2_WRITE_STATUS 0x00000020
+
+#define EFI_FVB2_LOCK_CAP 0x00000040
+#define EFI_FVB2_LOCK_STATUS 0x00000080
+
+#define EFI_FVB2_STICKY_WRITE 0x00000200
+#define EFI_FVB2_MEMORY_MAPPED 0x00000400
+#define EFI_FVB2_ERASE_POLARITY 0x00000800
+
+#define EFI_FVB2_READ_LOCK_CAP 0x00001000
+#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
+
+#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
+#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
+#define EFI_FVB2_ALIGNMENT 0x00170000
+#define EFI_FVB2_WEAK_ALIGNMENT 0x80000000
+
+#define EFI_FVB2_ALIGNMENT_1 0x00000000
+#define EFI_FVB2_ALIGNMENT_2 0x00010000
+#define EFI_FVB2_ALIGNMENT_4 0x00020000
+#define EFI_FVB2_ALIGNMENT_8 0x00030000
+#define EFI_FVB2_ALIGNMENT_16 0x00040000
+#define EFI_FVB2_ALIGNMENT_32 0x00050000
+#define EFI_FVB2_ALIGNMENT_64 0x00060000
+#define EFI_FVB2_ALIGNMENT_128 0x00070000
+#define EFI_FVB2_ALIGNMENT_256 0x00080000
+#define EFI_FVB2_ALIGNMENT_512 0x00090000
+#define EFI_FVB2_ALIGNMENT_1K 0x000a0000
+#define EFI_FVB2_ALIGNMENT_2K 0x000b0000
+#define EFI_FVB2_ALIGNMENT_4K 0x000c0000
+#define EFI_FVB2_ALIGNMENT_8K 0x000d0000
+#define EFI_FVB2_ALIGNMENT_16K 0x000e0000
+#define EFI_FVB2_ALIGNMENT_32K 0x000f0000
+#define EFI_FVB2_ALIGNMENT_64K 0x00100000
+#define EFI_FVB2_ALIGNMENT_128K 0x00110000
+#define EFI_FVB2_ALIGNMENT_256K 0x00120000
+#define EFI_FVB2_ALIGNMENT_512K 0x00130000
+#define EFI_FVB2_ALIGNMENT_1M 0x00140000
+#define EFI_FVB2_ALIGNMENT_2M 0x00150000
+#define EFI_FVB2_ALIGNMENT_4M 0x00160000
+#define EFI_FVB2_ALIGNMENT_8M 0x00170000
+#define EFI_FVB2_ALIGNMENT_16M 0x00180000
+#define EFI_FVB2_ALIGNMENT_32M 0x00190000
+#define EFI_FVB2_ALIGNMENT_64M 0x001a0000
+#define EFI_FVB2_ALIGNMENT_128M 0x001b0000
+#define EFI_FVB2_ALIGNMENT_256M 0x001c0000
+#define EFI_FVB2_ALIGNMENT_512M 0x001d0000
+#define EFI_FVB2_ALIGNMENT_1G 0x001e0000
+#define EFI_FVB2_ALIGNMENT_2G 0x001f0000
+
+/* SPI firmware volume and fmap related functions -
+ * This set of functions is based on the EFI firmware volume block2 protocol.
+ */
+uint32_t spi_get_fv_attribute(void);
+size_t spi_get_fv_blocksize(void);
+
+/* These functions translate fmap related requests to SPI related requests. */
+int spi_read_fmap_region(const char *name, uint32_t offset, size_t size, void *buffer);
+int spi_write_fmap_region(const char *name, uint32_t offset, size_t size, void *buffer);
+int spi_erase_fmap_region(const char *name, uint32_t offset, size_t size);
+
#endif /* __AMD_SPI_H__ */
diff --git a/src/soc/amd/common/block/spi/spi.c b/src/soc/amd/common/block/spi/spi.c
index 9bff570..34c973f 100644
--- a/src/soc/amd/common/block/spi/spi.c
+++ b/src/soc/amd/common/block/spi/spi.c
@@ -21,6 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
+#include <fmap.h>
#include <spi_flash.h>
#include <spi-generic.h>
#include <amdblocks/spi.h>
@@ -44,6 +45,107 @@
spi_flash_volatile_group_end(flash);
}
+
+/* SPI firmware volume related routines */
+
+/* Return the firmware volume attributes. These are currently fixed. */
+uint32_t spi_get_fv_attribute(void)
+{
+ return SPI_FV_ATTRIBUTES;
+}
+
+/* Return the erasable block size */
+size_t spi_get_fv_blocksize(void)
+{
+ struct spi_flash *flash = NULL;
+ int retval = spi_flash_probe(0, 0, flash);
+ if (retval) {
+ printk(BIOS_DEBUG, "Could not find SPI device\n");
+ return 0;
+ }
+
+ return flash->sector_size;
+}
+
+/* Memory mapped SPI access routines -
+ * These routines access the SPI through its memory mapped interface.
+ */
+
+int spi_read_fmap_region(const char *name, uint32_t offset, size_t size, void *buffer)
+{
+ struct spi_flash *flash = NULL;
+ struct region *area = NULL;
+ uint32_t spi_offset;
+
+ int retval = spi_flash_probe(0, 0, flash);
+ if (retval) {
+ printk(BIOS_DEBUG, "Could not find SPI device\n");
+ return -3;
+ }
+
+ if (fmap_locate_area(name, area)) {
+ printk(BIOS_DEBUG, "SPI FV region not found %s\n",name);
+ return -1;
+ };
+
+ if (offset + size > area->size) {
+ printk(BIOS_DEBUG, "SPI FV read upper bound violation\n");
+ return -2;
+ }
+
+ spi_offset = area->offset + offset + CONFIG_ROM_SIZE;
+ return spi_flash_read(flash, spi_offset, size, buffer);
+}
+
+int spi_write_fmap_region(const char *name, uint32_t offset, size_t size, void *buffer)
+{
+ struct spi_flash *flash = NULL;
+ struct region *area = NULL;
+ uint32_t spi_offset;
+
+ int retval = spi_flash_probe(0, 0, flash);
+ if (retval) {
+ printk(BIOS_DEBUG, "Could not find SPI device\n");
+ return -3;
+ }
+
+ if (fmap_locate_area(name, area)) {
+ printk(BIOS_DEBUG, "SPI FV region not found %s\n",name);
+ return -1;
+ };
+
+ if (offset + size > area->size) {
+ printk(BIOS_DEBUG, "SPI FV write upper bound violation\n");
+ return -2;
+ }
+
+ spi_offset = area->offset + offset + CONFIG_ROM_SIZE;
+ return spi_flash_write(flash, spi_offset, size, buffer);
+}
+
+int spi_erase_fmap_region(const char *name, uint32_t offset, size_t size)
+{
+ struct spi_flash *flash = NULL;
+ struct region *area = NULL;
+ uint32_t spi_offset;
+
+ int retval = spi_flash_probe(0, 0, flash);
+ if (retval) {
+ printk(BIOS_DEBUG, "Could not find SPI device\n");
+ return -3;
+ }
+
+ if (fmap_locate_area(name, area)) {
+ printk(BIOS_DEBUG, "SPI FV region not found %s\n",name);
+ return -1;
+ };
+ spi_offset = area->offset + offset + CONFIG_ROM_SIZE;
+ return spi_flash_erase(flash, spi_offset, size);
+}
+
+/* SPI alternate access mechanism -
+ * These routines access the SPI through its PCI register based interface.
+ */
static uintptr_t spibar;
@@ -136,6 +238,7 @@
return 0;
}
+/* TODO: Update these two routines to work with S3 */
int chipset_volatile_group_begin(const struct spi_flash *flash)
{
if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM))
--
To view, visit https://review.coreboot.org/22065
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I32208a214a6896308833ff34d459d5513b60ba7a
Gerrit-Change-Number: 22065
Gerrit-PatchSet: 1
Gerrit-Owner: John E. Kabat Jr. <john.kabat at scarletltd.com>
Gerrit-Reviewer: frank vibrans <frank.vibrans at scarletltd.com>
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