[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/pmc: Move pmc_disable_all_gpe to romstage

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22033


Change subject: soc/intel/common/block/pmc: Move pmc_disable_all_gpe to romstage
......................................................................

soc/intel/common/block/pmc: Move pmc_disable_all_gpe to romstage

Instead of disabling all GPEs during PMC init in bootblock, this
change moves it to pmc_fill_power_state which allows romstage to
correctly fill up GPE_EN registers in chipset_power_state. This is
essential for correctly identifying the wake source.

Disabling all GPEs was added recently in change 74145f76
(intel/common/pmc: Disable all GPEs during pmc_init) because keeping
GPEs enabled in coreboot while enabling SMI could lead to
side-effects as explained in the change. Moving pmc_disable_all_gpe to
pmc_fill_power_state should be safe as that happens before SMI is
enabled in coreboot.

TEST=Verified that GPE-based wake source is correctly
identified. Also, no issues observed while resuming from S3.

Change-Id: I8e992ad09ffdefba62de11fa572e783715776bf1
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 5 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/22033/1

diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index 9dbac24..89c3cdc 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -149,7 +149,9 @@
 
 /*
  * Reads and prints ACPI specific PM registers which are common across
- * chipsets. Returns the previous sleep state which is one of ACPI_SX values.
+ * chipsets. Returns the previous sleep state which is one of ACPI_SX
+ * values. Additionally, it also disables all GPEs after GPE_EN
+ * registers are read.
  */
 int pmc_fill_power_state(struct chipset_power_state *ps);
 
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index b8ec17d..e78eb79 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -410,6 +410,8 @@
 	ps->prev_sleep_state = pmc_prev_sleep_state(ps);
 	printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
 
+	pmc_disable_all_gpe();
+
 	return ps->prev_sleep_state;
 }
 
@@ -558,6 +560,4 @@
 
 	/* Set the routes in the GPIO communities as well. */
 	gpio_route_gpe(dw0, dw1, dw2);
-
-	pmc_disable_all_gpe();
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8e992ad09ffdefba62de11fa572e783715776bf1
Gerrit-Change-Number: 22033
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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