[coreboot-gerrit] Change in coreboot[master]: intel/cannonlake_rvp: Declare PCIE clock usage

[Lijian Zhao (Code Review)]

Hello Subrata Banik, AndreX Andraos, John Zhao, Bora Guvendik, build bot (Jenkins), Hannah Williams, Shaunak Saha, Krzysztof M Sywula, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/21879

to look at the new patch set (#4).

Change subject: intel/cannonlake_rvp: Declare PCIE clock usage
......................................................................

intel/cannonlake_rvp: Declare PCIE clock usage

Define PCI express clock usage for cannonlake u and cannonlake y rvp
based on board design.

TEST=Bootable into OS.

Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
2 files changed, 32 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/21879/4
-- 
To view, visit https://review.coreboot.org/21879
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4
Gerrit-Change-Number: 21879
Gerrit-PatchSet: 4
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: AndreX Andraos <andrex.andraos at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: John Zhao <john.zhao at intel.com>
Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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