[coreboot-gerrit] Change in coreboot[master]: soraka:[DEBUGONLY] Disable LTR for Wifi

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/21870


Change subject: soraka:[DEBUGONLY] Disable LTR for Wifi
......................................................................

soraka:[DEBUGONLY] Disable LTR for Wifi

Change-Id: Id757b287f841265829dec63774fa76b506b7165e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/21870/1

diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 902b202..5879c6f 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -155,7 +155,7 @@
 	# RP 1, Enable Advanced Error Reporting
 	register "PcieRpAdvancedErrorReporting[0]" = "0"
 	# RP 1, Enable Latency Tolerance Reporting Mechanism
-	register "PcieRpLtrEnable[0]" = "1"
+	register "PcieRpLtrEnable[0]" = "0"
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port

-- 
To view, visit https://review.coreboot.org/21870
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id757b287f841265829dec63774fa76b506b7165e
Gerrit-Change-Number: 21870
Gerrit-PatchSet: 1
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20171004/bd27de65/attachment.html>