[coreboot-gerrit] Change in coreboot[master]: src/device: Update LTR configuration scheme

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/21868


Change subject: src/device: Update LTR configuration scheme
......................................................................

src/device: Update LTR configuration scheme

This patch moves out LTR programming under L1 substate
to pchexp_tune_device function, as substate programming
and LTR programming are independent.

LTR programming scheme is updated to check LTR is enabled
and supported for entire link and only then LTR for device
needs to be enabled to comply with PCI base specification
(rev 3.1a, section 6.18). And remove explicit LTR enable
programming for root device under L1 substate.

BRANCH=none
BUG=b:66722364
TEST=Verify LTR is configured for end point device only
when all parent devices in link has LTR enabled and max
snoop latency gets configured.

Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/device/pciexp_device.c
M src/include/device/pci_def.h
2 files changed, 43 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21868/1

diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 40c3f8c..e3859d8 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -149,16 +149,49 @@
 			root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4);
 }
 
-static void pciexp_enable_ltr(device_t dev)
+static unsigned int pciexp_is_ltrenable(device_t dev)
 {
 	unsigned int cap;
 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
-	if(!cap) {
+	if (cap && pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET) &
+			1 << 11 && pci_read_config16(dev, cap
+				+PCI__EXP_DEV_CTL_STS2_CAP_OFFSET) & 1 << 10)
+		return 1;
+
+	return 0;
+}
+
+static void pciexp_enable_ltr(device_t dev)
+{
+	unsigned int cap;
+	device_t root;
+
+	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
+	/* Check if capibility pointer is valid and  dev ltrms is enabled*/
+	if (!cap && pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET) &
+			1 << 11) {
 		printk(BIOS_INFO, "Failed to enable LTR for dev = %s\n",
 			dev_path(dev));
 		return;
 	}
-	pci_update_config32(dev, cap + 0x28, ~(1 << 10), 1 << 10);
+	for (root = dev->bus->dev; root->path.type != DEVICE_PATH_DOMAIN;
+			root = root->bus->dev) {
+		if (pciexp_is_ltrenable(root))
+			continue;
+		break;
+	}
+	if (root->path.type == DEVICE_PATH_DOMAIN) {
+		pci_update_config32(dev, cap +
+				PCI__EXP_DEV_CTL_STS2_CAP_OFFSET,
+				~(1 << 10), 1 << 10);
+		pciexp_config_max_latency(dev->bus->dev, dev);
+	}
+	else
+		printk(BIOS_INFO,
+				" Failed to enable LTR for dev %s"
+				"as link ltr support is disabled\n",
+				dev_path(dev));
+	return;
 }
 
 static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap,
@@ -232,8 +265,6 @@
 	printk(BIOS_INFO, "Power On Value = 0x%x, Power On Scale = 0x%x\n",
 		endp_power_on_value, power_on_scale);
 
-	pciexp_enable_ltr(root);
-
 	pci_update_config32(root, root_cap + 0x08, ~0xff00,
 		(comm_mode_rst_time << 8));
 
@@ -255,10 +286,6 @@
 
 		pci_update_config32(dev_t, end_cap + 0x08, ~0x1f,
 			L1SubStateSupport);
-
-		pciexp_enable_ltr(dev_t);
-
-		pciexp_config_max_latency(root, dev_t);
 	}
 }
 
@@ -391,6 +418,9 @@
 	if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))
 		pciexp_config_L1_sub_state(root, dev);
 
+	/* Check for LTR support and enable */
+	pciexp_enable_ltr(dev);
+
 	/* Check for and enable ASPM */
 	if (IS_ENABLED(CONFIG_PCIEXP_ASPM))
 		pciexp_enable_aspm(root, root_cap, dev, cap);
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 1674ee1..a7e032c 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -373,6 +373,10 @@
 #define PCI_EXP_DEVCAP		4	/* Device capabilities */
 #define  PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
 #define  PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
+/* Device Capabilities 2 offset */
+#define  PCI_EXP_DEV_CAP2_OFFSET	0x24
+/* Device Control Status 2  offset*/
+#define  PCI__EXP_DEV_CTL_STS2_CAP_OFFSET	0x28
 #define  PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
 #define  PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
 #define  PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe
Gerrit-Change-Number: 21868
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
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