[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Clarify SPD structure in chip.h

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21852


Change subject: amd/stoneyridge: Clarify SPD structure in chip.h
......................................................................

amd/stoneyridge: Clarify SPD structure in chip.h

Add #define values and clarify the spdAddrLookup array.

Change-Id: I39b9913a2fd52f9105e4a771f651a8d9649202e6
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/chip.h
1 file changed, 6 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/21852/1

diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index 216a819..01127b0 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -18,6 +18,10 @@
 
 #include <stdint.h>
 
+#define MAX_NODES 1
+#define MAX_DRAM_CH 1
+#define MAX_DIMMS_PER_CH 2
+
 struct soc_amd_stoneyridge_config {
 	u32 uma_mode;
 		/* Do not enable UMA in the system. */
@@ -43,7 +47,8 @@
 		#define UMATYPE_NONLEGACY 1
 	/* Size in units of 64KB, N/A for none and auto */
 	u32 uma_size;
-	u8 spdAddrLookup[1][1][2];
+
+	u8 spdAddrLookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
 	u32 ide0_enable : 1;
 	u32 sata0_enable : 1;
 	u32 boot_switch_sata_ide : 1;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I39b9913a2fd52f9105e4a771f651a8d9649202e6
Gerrit-Change-Number: 21852
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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