[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Remove 16MB cbmem assert

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21850


Change subject: amd/stoneyridge: Remove 16MB cbmem assert
......................................................................

amd/stoneyridge: Remove 16MB cbmem assert

Do not check for the top of memory being 16MB-aligned near the end of
romstage.  This is not the expected alignment using the default 8MB SMM
region size.

BUG=b:67320715

Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/romstage.c
1 file changed, 1 insertion(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21850/1

diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 8cd4d43..7b86a3d 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -88,8 +88,7 @@
 	 * 16 megs under cbmem top which is a safe bet to cover ramstage.
 	 */
 	top_of_ram = (uintptr_t) cbmem_top();
-	/* cbmem_top() needs to be at least 16 MiB aligned */
-	assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
+
 	postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
 		MTRR_TYPE_WRBACK);
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119
Gerrit-Change-Number: 21850
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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