[coreboot-gerrit] Change in coreboot[master]: superio/ite/common: Add temperature offset
Vagiz Tarkhanov (Code Review)
gerrit at coreboot.org
Mon Oct 2 17:18:31 CEST 2017
Vagiz Tarkhanov has uploaded this change for review. ( https://review.coreboot.org/21843
Change subject: superio/ite/common: Add temperature offset
......................................................................
superio/ite/common: Add temperature offset
Add devicetree options to set temperature adjustment registers
required for thermal diode sensors and PECI.
Without these adjustmets thermal diode sensors and PECI display raw
values. For PECI it means negative temperatures.
I'd gladly update TMPINx shorthands to FANx format, but many boards
already assume that TMPINx set mode.
Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Signed-off-by: Vagiz Tarkhanov <rakkin at autistici.org>
---
M src/superio/ite/common/env_ctrl.c
M src/superio/ite/common/env_ctrl.h
M src/superio/ite/common/env_ctrl_chip.h
3 files changed, 47 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/21843/1
diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c
index 1e313ce..5f216c1 100644
--- a/src/superio/ite/common/env_ctrl.c
+++ b/src/superio/ite/common/env_ctrl.c
@@ -99,13 +99,13 @@
* into TMPINx register
*/
static void enable_tmpin(const u16 base, const u8 tmpin,
- const enum ite_ec_thermal_mode mode)
+ const struct ite_ec_thermal_config *const conf)
{
u8 reg;
reg = ite_ec_read(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE);
- switch (mode) {
+ switch (conf->mode) {
case THERMAL_DIODE:
reg |= ITE_EC_ADC_TEMP_DIODE_MODE(tmpin);
break;
@@ -115,11 +115,17 @@
default:
printk(BIOS_WARNING,
"Unsupported thermal mode 0x%x on TMPIN%d\n",
- mode, tmpin);
+ conf->mode, tmpin);
return;
}
ite_ec_write(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg);
+
+ /* Set temperature offsets */
+ reg = ite_ec_read(base, ITE_EC_BEEP_ENABLE);
+ reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE;
+ ite_ec_write(base, ITE_EC_BEEP_ENABLE, reg);
+ ite_ec_write(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset);
/* Enable the startup of monitoring operation */
reg = ite_ec_read(base, ITE_EC_CONFIGURATION);
@@ -233,7 +239,7 @@
/* Enable HWM if configured */
for (i = 0; i < ITE_EC_TMPIN_CNT; ++i)
- enable_tmpin(base, i + 1, conf->tmpin_mode[i]);
+ enable_tmpin(base, i + 1, &conf->tmpin[i]);
/* Enable reading of voltage pins */
ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask);
diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h
index fa13116..1be6436 100644
--- a/src/superio/ite/common/env_ctrl.h
+++ b/src/superio/ite/common/env_ctrl.h
@@ -93,6 +93,26 @@
#define ITE_EC_ADC_TEMP_DIODE_MODE(x) (1 << ((x)-1))
#define ITE_EC_ADC_TEMP_EXTRA_CHANNEL_ENABLE 0x55
+/* Matches length of ITE_EC_TMPIN_CNT */
+static const u8 ITE_EC_TEMP_ADJUST[] = { 0x56, 0x57, 0x59 };
+
+#define ITE_EC_BEEP_ENABLE 0x5C
+#define ITE_EC_TEMP_ADJUST_WRITE_ENABLE (1 << 7)
+#define ITE_EC_ADC_CLOCK_1MHZ (6 << 4)
+#define ITE_EC_ADC_CLOCK_2MHZ (7 << 4)
+#define ITE_EC_ADC_CLOCK_24MHZ (5 << 4)
+#define ITE_EC_ADC_CLOCK_31KHZ (4 << 4)
+#define ITE_EC_ADC_CLOCK_62KHZ (3 << 4)
+#define ITE_EC_ADC_CLOCK_125KHZ (2 << 4)
+#define ITE_EC_ADC_CLOCK_250KHZ (1 << 4)
+#define ITE_EC_ADC_CLOCK_500KHZ (0 << 4)
+#define ITE_EC_BEEP_ON_TMP_LIMIT (1 << 2)
+#define ITE_EC_BEEP_ON_VIN_LIMIT (1 << 1)
+#define ITE_EC_BEEP_ON_FAN_LIMIT (1 << 0)
+#define ITE_EC_BEEP_FREQ_DIV_OF_FAN 0x5D
+#define ITE_EC_BEEP_FREQ_DIV_OF_VOLT 0x5E
+#define ITE_EC_BEEP_FREQ_DIV_OF_TEMP 0x5F
+
#define ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(x) (0x60 + ((x)-1) * 8)
#define ITE_EC_FAN_CTL_TEMP_LIMIT_START(x) (0x61 + ((x)-1) * 8)
#define ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(x) (0x62 + ((x)-1) * 8)
diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h
index f01c574..a1bb89d 100644
--- a/src/superio/ite/common/env_ctrl_chip.h
+++ b/src/superio/ite/common/env_ctrl_chip.h
@@ -28,6 +28,12 @@
THERMAL_RESISTOR,
};
+struct ite_ec_thermal_config {
+ enum ite_ec_thermal_mode mode;
+ /* Offset is used for diode sensors and PECI */
+ u8 offset;
+};
+
/* Bit mask for voltage pins VINx */
enum ite_ec_voltage_pin {
VIN0 = 0x01,
@@ -74,25 +80,28 @@
u8 peci_tmpin;
/*
- * Enable thermal mode on TMPINx.
- */
- enum ite_ec_thermal_mode tmpin_mode[ITE_EC_TMPIN_CNT];
-
- /*
* Enable reading of voltage pins VINx.
*/
enum ite_ec_voltage_pin vin_mask;
/*
+ * Enable temperature sensors in given mode.
+ */
+ struct ite_ec_thermal_config tmpin[ITE_EC_TMPIN_CNT];
+
+ /*
* Enable a FAN in given mode.
*/
struct ite_ec_fan_config fan[ITE_EC_FAN_CNT];
+
+ /* FIXME: enable beep when exceeding TMPIN, VIN, FAN limits */
};
/* Some shorthands for device trees */
-#define TMPIN1 ec.tmpin_mode[0]
-#define TMPIN2 ec.tmpin_mode[1]
-#define TMPIN3 ec.tmpin_mode[2]
+#define TMPIN1 ec.tmpin[0].mode
+#define TMPIN2 ec.tmpin[1].mode
+#define TMPIN3 ec.tmpin[2].mode
+
#define FAN1 ec.fan[0]
#define FAN2 ec.fan[1]
#define FAN3 ec.fan[2]
--
To view, visit https://review.coreboot.org/21843
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Gerrit-Change-Number: 21843
Gerrit-PatchSet: 1
Gerrit-Owner: Vagiz Tarkhanov <rakkin at autistici.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20171002/530eaadb/attachment.html>
More information about the coreboot-gerrit
mailing list