[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Tell FSPM UART port number

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22655


Change subject: soc/intel/cannonlake: Tell FSPM UART port number
......................................................................

soc/intel/cannonlake: Tell FSPM UART port number

Cannonlake FSP will send debug message on selected UART port, use same
coreboot UART debug port to FSP.

TEST=Boot up with board have UART port 0 and can see the print of FSP

Change-Id: Id72e459d2fbb1f16b005d22fac66667086880384
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/romstage/romstage.c
1 file changed, 1 insertion(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/22655/1

diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 94b54a6..8b3794f 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -92,6 +92,7 @@
 	m_cfg->EnableC6Dram = config->enable_c6dram;
 	/* Disable Cpu Ratio Override temporary. */
 	m_cfg->CpuRatio = 0;
+	m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id72e459d2fbb1f16b005d22fac66667086880384
Gerrit-Change-Number: 22655
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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