[coreboot-gerrit] Change in coreboot[master]: intel/bd82x6x: Refactor and complete IRQ routing
Tobias Diedrich (Code Review)
gerrit at coreboot.org
Sat Nov 25 23:06:49 CET 2017
Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22601
Change subject: intel/bd82x6x: Refactor and complete IRQ routing
......................................................................
intel/bd82x6x: Refactor and complete IRQ routing
Refactor the irq routing to use a single source of truth for consistency.
Add missing routing data for the gigabit ethernet and management engine devices.
Apply the good old PCI strategy of rotating the list links by one for each pci device (since most devices use link A this works well).
Also fix small mistake in DIR_ROUTE, the register is 16-bits wide.
If the DIR_ROUTE call ordering was reversed the previous writes would get overwritten.
With this, the built-in gigabit ethernet works with pci=nomsi in Linux.
Change-Id: I7229aee3817f1f4979325a2abccbb3b99ad312f6
Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
M src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
A src/southbridge/intel/bd82x6x/acpi/default_irq_route.h
M src/southbridge/intel/bd82x6x/early_rcba.c
M src/southbridge/intel/bd82x6x/pch.h
4 files changed, 83 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/22601/1
diff --git a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
index 0e6f960..dc4c300 100644
--- a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
@@ -14,64 +14,37 @@
* GNU General Public License for more details.
*/
+#define APIC_PIRQA 16
+#define APIC_PIRQB 17
+#define APIC_PIRQC 18
+#define APIC_PIRQD 19
+#define APIC_PIRQE 20
+#define APIC_PIRQF 21
+#define APIC_PIRQG 22
+#define APIC_PIRQH 23
+
/* PCI Interrupt Routing */
Method(_PRT)
{
If (PICM) {
Return (Package() {
- /* Onboard graphics (IGD) 0:2.0 */
- Package() { 0x0002ffff, 0, 0, 16 },/* GFX INTA -> PIRQA (MSI) */
- /* PCI Express Graphics (PEG) 0:1.0 */
- Package() { 0x0001ffff, 0, 0, 16 },/* GFX PCIe INTA -> PIRQA (MSI) */
- Package() { 0x0001ffff, 0, 0, 17 },/* GFX PCIe INTB -> PIRQB (MSI) */
- Package() { 0x0001ffff, 0, 0, 18 },/* GFX PCIe INTC -> PIRQC (MSI) */
- Package() { 0x0001ffff, 0, 0, 19 },/* GFX PCIe INTD -> PIRQD (MSI) */
- /* XHCI 0:14.0 (ivy only) */
- Package() { 0x0014ffff, 0, 0, 19 },
- /* High Definition Audio 0:1b.0 */
- Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */
- /* PCIe Root Ports 0:1c.x */
- Package() { 0x001cffff, 0, 0, 17 },/* D28IP_P1IP PCIe INTA -> PIRQB */
- Package() { 0x001cffff, 1, 0, 21 },/* D28IP_P2IP PCIe INTB -> PIRQF */
- Package() { 0x001cffff, 2, 0, 19 },/* D28IP_P3IP PCIe INTC -> PIRQD */
- Package() { 0x001cffff, 3, 0, 20 },/* D28IP_P3IP PCIe INTD -> PIRQE */
- /* EHCI #1 0:1d.0 */
- Package() { 0x001dffff, 0, 0, 19 },/* D29IP_E1P EHCI1 INTA -> PIRQD */
- /* EHCI #2 0:1a.0 */
- Package() { 0x001affff, 0, 0, 21 },/* D26IP_E2P EHCI2 INTA -> PIRQF */
- /* LPC devices 0:1f.0 */
- Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */
- Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */
- Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */
- Package() { 0x001fffff, 3, 0, 18 },
+#define PCI_DEV_PIRQ_ROUTES(dev_, pina_, pinb_, pinc_, pind_) \
+ Package() { ## dev_ ## ffff, 0, 0, APIC_PIRQ ## pina_ }, \
+ Package() { ## dev_ ## ffff, 1, 0, APIC_PIRQ ## pinb_ }, \
+ Package() { ## dev_ ## ffff, 2, 0, APIC_PIRQ ## pinc_ }, \
+ Package() { ## dev_ ## ffff, 3, 0, APIC_PIRQ ## pind_ },
+#include "default_irq_route.h"
})
} Else {
Return (Package() {
- /* Onboard graphics (IGD) 0:2.0 */
- Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- /* PCI Express Graphics (PEG) 0:1.0 */
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
- Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- /* XHCI 0:14.0 (ivy only) */
- Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- /* High Definition Audio 0:1b.0 */
- Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
- /* PCIe Root Ports 0:1c.x */
- Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
- Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
- Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
- /* EHCI #1 0:1d.0 */
- Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
- /* EHCI #2 0:1a.0 */
- Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
- /* LPC device 0:1f.0 */
- Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
- Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
- Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
- Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+#define PCI_DEV_PIRQ_ROUTES(dev_, pina_, pinb_, pinc_, pind_) \
+ Package() { ## dev_ ## ffff, 0, \_SB.PCI0.LPCB.LNK ## pina_, 0 }, \
+ Package() { ## dev_ ## ffff, 1, \_SB.PCI0.LPCB.LNK ## pinb_, 0 }, \
+ Package() { ## dev_ ## ffff, 2, \_SB.PCI0.LPCB.LNK ## pinc_, 0 }, \
+ Package() { ## dev_ ## ffff, 3, \_SB.PCI0.LPCB.LNK ## pind_, 0 },
+#include "default_irq_route.h"
})
}
}
+
+#undef PCI_DEV_PIRQ_ROUTES
diff --git a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.h b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.h
new file mode 100644
index 0000000..f2ee57b
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+PCI_DEV_PIRQ_ROUTES(0x02, A, B, C, D) /* IGD GFX */
+PCI_DEV_PIRQ_ROUTES(0x01, A, B, C, D) /* PCIe GFX */
+PCI_DEV_PIRQ_ROUTES(0x14, F, G, H, A) /* D20 XHCI (ivy only) */
+PCI_DEV_PIRQ_ROUTES(0x16, G, H, A, B) /* D22 MEI */
+PCI_DEV_PIRQ_ROUTES(0x19, H, A, B, C) /* D25 GBE */
+PCI_DEV_PIRQ_ROUTES(0x1a, A, B, C, D) /* D26 EHCI2 */
+PCI_DEV_PIRQ_ROUTES(0x1b, B, C, D, E) /* D27 HDA */
+PCI_DEV_PIRQ_ROUTES(0x1c, C, D, E, F) /* D28 PCIe */
+PCI_DEV_PIRQ_ROUTES(0x1d, D, E, F, G) /* D29 EHCI1 */
+PCI_DEV_PIRQ_ROUTES(0x1f, E, F, G, H) /* D31 LPC/SATA/SMBUS */
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index eeecb5f..9a9e7e8 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -15,48 +15,51 @@
* GNU General Public License for more details.
*/
+#include <console/console.h>
#include <stdint.h>
#include "pch.h"
#include "northbridge/intel/sandybridge/sandybridge.h"
+static inline void write_dir_route(u8 dev, u8 a, u8 b, u8 c, u8 d) {
+ switch (dev) {
+ case 0x01:
+ case 0x02:
+ printk(BIOS_WARNING, "Can't set PIRQs for dev 0x%02x\n", dev);
+ break;
+ case 0x14: DIR_ROUTE(D20IR, a, b, c, d); break;
+ case 0x16: DIR_ROUTE(D22IR, a, b, c, d); break;
+ case 0x19: DIR_ROUTE(D25IR, a, b, c, d); break;
+ case 0x1a: DIR_ROUTE(D26IR, a, b, c, d); break;
+ case 0x1b: DIR_ROUTE(D27IR, a, b, c, d); break;
+ case 0x1c: DIR_ROUTE(D28IR, a, b, c, d); break;
+ case 0x1d: DIR_ROUTE(D29IR, a, b, c, d); break;
+ case 0x1f: DIR_ROUTE(D31IR, a, b, c, d); break;
+ default:
+ printk(BIOS_WARNING, "PIRQs for unknown dev 0x%02x\n", dev);
+ break;
+ }
+}
+
void
southbridge_configure_default_intmap(void)
{
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP SLOT1 INTA -> PIRQB
- * D28IP_P2IP SLOT2 INTB -> PIRQF
- * D28IP_P3IP SLOT3 INTC -> PIRQD
- * D28IP_P5IP SLOT5 INTC -> PIRQD
- * D29IP_E1P EHCI1 INTA -> PIRQD
- * D26IP_E2P EHCI2 INTA -> PIRQF
- * D31IP_SIP SATA INTA -> PIRQB (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQH
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQA (MSI)
- *
-
- */
-
- RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ /* PCI interupt pin defaults. */
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (INTD << D31IP_SIP2) |
(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
- RCBA32(D30IP) = (NOINT << D30IP_PIP);
+ RCBA32(D30IP) = (NOINT << D30IP_PIP); /* PCI bridge is never
+used */
RCBA32(D29IP) = (INTA << D29IP_E1P);
RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
(INTC << D28IP_P3IP) | (INTC << D28IP_P5IP);
RCBA32(D27IP) = (INTA << D27IP_ZIP);
RCBA32(D26IP) = (INTA << D26IP_E2P);
- RCBA32(D25IP) = (NOINT << D25IP_LIP);
- RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+ RCBA32(D25IP) = (INTA << D25IP_LIP);
+ RCBA32(D22IP) = (INTA << D22IP_MEI1IP);
/* Device interrupt route registers */
- DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
- DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
- DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
- DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
- DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
- DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
- DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+#define PCI_DEV_PIRQ_ROUTES(dev_, pina_, pinb_, pinc_, pind_) \
+ write_dir_route(dev_, PIRQ ## pina_, PIRQ ## pinb_, PIRQ ## pinc_, PIRQ ## pind_);
+#include "acpi/default_irq_route.h"
/* Enable IOAPIC (generic) */
RCBA16(OIC) = 0x0100;
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 51f3b94..0b16bdc 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -376,6 +376,7 @@
#define D31IP 0x3100 /* 32bit */
#define D31IP_TTIP 24 /* Thermal Throttle Pin */
#define D31IP_SIP2 20 /* SATA Pin 2 */
+#define D31IP_RSVD 16 /* Reserved */
#define D31IP_SMIP 12 /* SMBUS Pin */
#define D31IP_SIP 8 /* SATA Pin */
#define D30IP 0x3104 /* 32bit */
@@ -418,7 +419,7 @@
#define SOFT_RESET_DATA 0x38f8
#define DIR_ROUTE(x,a,b,c,d) \
- RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+ RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
((b) << DIR_IBR) | ((a) << DIR_IAR))
#define RC 0x3400 /* 32bit */
--
To view, visit https://review.coreboot.org/22601
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7229aee3817f1f4979325a2abccbb3b99ad312f6
Gerrit-Change-Number: 22601
Gerrit-PatchSet: 1
Gerrit-Owner: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
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