[coreboot-gerrit] Change in coreboot[master]: acpi/tpm: remove non-existent IRQ for Infineon TPM chip

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/22582


Change subject: acpi/tpm: remove non-existent IRQ for Infineon TPM chip
......................................................................

acpi/tpm: remove non-existent IRQ for Infineon TPM chip

The Infineon TPM chip used on these platforms doesn't use an IRQ
line; the Linux kernel has patched to work around this, but better
to remove it completely.

Change-Id: Id510c73cfdc14b7f82b0cc695691b55423185a0b
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/baytrail/acpi/lpc.asl
M src/soc/intel/braswell/acpi/lpc.asl
M src/soc/intel/fsp_baytrail/acpi/lpc.asl
M src/southbridge/intel/i82801gx/acpi/lpc.asl
M src/southbridge/intel/lynxpoint/acpi/lpc.asl
5 files changed, 0 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22582/1

diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index 23048f2..17d6f43 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -155,7 +155,6 @@
 			IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
 			IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
 			Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
-			IRQ (Edge, Activehigh, Exclusive) { 6 }
 		})
 	}
 #endif
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index e6b8cc9..eb4a16a 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -157,7 +157,6 @@
 			IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
 			IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
 			Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
-			IRQ (Edge, Activehigh, Exclusive) { 6 }
 		})
 	}
 #endif
diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
index 23048f2..17d6f43 100644
--- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
@@ -155,7 +155,6 @@
 			IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
 			IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
 			Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
-			IRQ (Edge, Activehigh, Exclusive) { 6 }
 		})
 	}
 #endif
diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl
index f080b6a..2bcd06f 100644
--- a/src/southbridge/intel/i82801gx/acpi/lpc.asl
+++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl
@@ -218,7 +218,6 @@
 			IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
 			IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
 			Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
-			IRQ (Edge, Activehigh, Exclusive) { 6 }
 		})
 	}
 #endif
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
index 3e13ac3..1df49e3 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
@@ -243,7 +243,6 @@
 			IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
 			IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
 			Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
-			IRQ (Edge, Activehigh, Exclusive) { 6 }
 		})
 	}
 #endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id510c73cfdc14b7f82b0cc695691b55423185a0b
Gerrit-Change-Number: 22582
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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