[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Delete early_setup.c
Richard Spiegel (Code Review)
gerrit at coreboot.org
Wed Nov 22 22:36:41 CET 2017
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22569
Change subject: amd/stoneyridge: Delete early_setup.c
......................................................................
amd/stoneyridge: Delete early_setup.c
Delete early_setup.c, Change kahlee/ec.c to use new southbridge.c function
sb_set_wideio_range. Remove <#ifdef __PRE_RAM__> from kahlee/ec.c.
BUG=b:64033893
Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/mainboard/google/kahlee/ec.c
M src/soc/amd/stoneyridge/Makefile.inc
D src/soc/amd/stoneyridge/early_setup.c
3 files changed, 6 insertions(+), 120 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/22569/1
diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c
index 3f309eb..35246c9 100644
--- a/src/mainboard/google/kahlee/ec.c
+++ b/src/mainboard/google/kahlee/ec.c
@@ -36,9 +36,9 @@
static void early_ec_init(void)
{
-#ifdef __PRE_RAM__
uint16_t ec_ioport_base;
size_t ec_ioport_size;
+ uint8_t status;
/*
* Set up LPC decoding for the ChromeEC I/O port ranges:
@@ -50,8 +50,11 @@
printk(BIOS_DEBUG,
"LPC Setup google_chromeec_ioport_range: %04x, %08zx\n",
ec_ioport_base, ec_ioport_size);
- lpc_wideio_512_window(ec_ioport_base);
-#endif //_PRE_RAM_
+ status = sb_set_wideio_range(ec_ioport_base, ec_ioport_size);
+ if (status == WIDE_IO_RANGE_FAILED)
+ printk(BIOS_DEBUG, "Failed to assign a range\n");
+ else
+ printk(BIOS_DEBUG, "Range assigned to wide IO %d\n", status);
}
void mainboard_ec_init(void)
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index f513a20..a978a75 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -40,14 +40,12 @@
bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
bootblock-y += BiosCallOuts.c
bootblock-y += bootblock/bootblock.c
-bootblock-y += early_setup.c
bootblock-y += pmutil.c
bootblock-y += tsc_freq.c
bootblock-y += southbridge.c
romstage-y += BiosCallOuts.c
romstage-y += romstage.c
-romstage-y += early_setup.c
romstage-y += dimmSpd.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
romstage-y += gpio.c
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c
deleted file mode 100644
index 09eb8b6..0000000
--- a/src/soc/amd/stoneyridge/early_setup.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <agesawrapper.h>
-#include <assert.h>
-#include <stdint.h>
-#include <arch/io.h>
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <reset.h>
-#include <arch/cpu.h>
-#include <cbmem.h>
-#include <soc/southbridge.h>
-#include <soc/pci_devs.h>
-#include <cpu/x86/msr.h>
-#include <delay.h>
-
-static void enable_wideio(uint8_t port, uint16_t size)
-{
- uint32_t wideio_enable[] = {
- LPC_WIDEIO0_ENABLE,
- LPC_WIDEIO1_ENABLE,
- LPC_WIDEIO2_ENABLE
- };
- uint32_t alt_wideio_enable[] = {
- LPC_ALT_WIDEIO0_ENABLE,
- LPC_ALT_WIDEIO1_ENABLE,
- LPC_ALT_WIDEIO2_ENABLE
- };
- pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
- uint32_t tmp;
-
- /* Only allow port 0-2 */
- assert(port <= ARRAY_SIZE(wideio_enable));
-
- if (size == 16) {
- tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE);
- tmp |= alt_wideio_enable[port];
- pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp);
- } else { /* 512 */
- tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE);
- tmp &= ~alt_wideio_enable[port];
- pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp);
- }
-
- /* Enable the range */
- tmp = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
- tmp |= wideio_enable[port];
- pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, tmp);
-}
-
-/*
- * lpc_wideio_window() may be called any point in romstage, but take
- * care that AGESA doesn't overwrite the range this function used.
- * The function checks if there is an empty range and if all ranges are
- * used the function throws an assert. The function doesn't check for a
- * duplicate range, for ranges that can be merged into a single
- * range, or ranges that overlap.
- *
- * The developer is expected to ensure that there are no conflicts.
- */
-static void lpc_wideio_window(uint16_t base, uint16_t size)
-{
- pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
- u32 tmp;
-
- /* Support 512 or 16 bytes per range */
- assert(size == 512 || size == 16);
-
- /* Find and open Base Register and program it */
- tmp = pci_read_config32(dev, LPC_WIDEIO_GENERIC_PORT);
-
- if ((tmp & 0xffff) == 0) { /* WIDEIO0 */
- tmp |= base;
- pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp);
- enable_wideio(0, size);
- } else if ((tmp & 0xffff0000) == 0) { /* WIDEIO1 */
- tmp |= (base << 16);
- pci_write_config32(dev, LPC_WIDEIO_GENERIC_PORT, tmp);
- enable_wideio(1, size);
- } else { /* Check WIDEIO2 register */
- tmp = pci_read_config32(dev, LPC_WIDEIO2_GENERIC_PORT);
- if ((tmp & 0xffff) == 0) { /* WIDEIO2 */
- tmp |= base;
- pci_write_config32(dev, LPC_WIDEIO2_GENERIC_PORT, tmp);
- enable_wideio(2, size);
- } else { /* All WIDEIO locations used*/
- assert(0);
- }
- }
-}
-
-void lpc_wideio_512_window(uint16_t base)
-{
- assert(IS_ALIGNED(base, 512));
- lpc_wideio_window(base, 512);
-}
-
-void lpc_wideio_16_window(uint16_t base)
-{
- assert(IS_ALIGNED(base, 16));
- lpc_wideio_window(base, 16);
-}
--
To view, visit https://review.coreboot.org/22569
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3
Gerrit-Change-Number: 22569
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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