[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Make use of Intel common PMC common block
Subrata Banik (Code Review)
gerrit at coreboot.org
Wed Nov 22 14:34:51 CET 2017
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22565
Change subject: soc/intel/skylake: Make use of Intel common PMC common block
......................................................................
soc/intel/skylake: Make use of Intel common PMC common block
TEST=Build and boot soraka/eve
Change-Id: I042bf62407b0acee3d24fbba2de2d482c3fbff9a
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/pmc.c
M src/soc/intel/skylake/romstage/Makefile.inc
D src/soc/intel/skylake/romstage/pmc.c
4 files changed, 36 insertions(+), 134 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/22565/1
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index da45ec5..0f9a417 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -37,6 +37,7 @@
romstage-y += me.c
romstage-y += pch.c
romstage-y += pei_data.c
+romstage-y += pmc.c
romstage-y += pmutil.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += spi.c
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index 9c05ff6..9d9d96f 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -3,7 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,25 +18,35 @@
#include <chip.h>
#include <console/console.h>
#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <arch/acpi.h>
-#include <cpu/cpu.h>
-#include <intelblocks/pcr.h>
+#include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h>
-#include <pc80/mc146818rtc.h>
+#include <intelblocks/rtc.h>
#include <reg_script.h>
-#include <string.h>
-#include <soc/gpio.h>
-#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <soc/pmc.h>
-#include <cpu/x86/smm.h>
-#include <soc/pcr_ids.h>
-#include <soc/ramstage.h>
+
+void pmc_set_disb(void)
+{
+ /* Set the DISB after DRAM init */
+ u32 disb_val = 0;
+ disb_val = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A);
+ disb_val |= DISB;
+
+ /* Don't clear bits that are write-1-to-clear */
+ disb_val &= ~(GBL_RST_STS | MS4V);
+ pci_write_config32(PCH_DEV_PMC, GEN_PMCON_A, disb_val);
+}
+
+/* Fill up PMC resource structure */
+void soc_pch_pmc_get_resources(struct pmc_resource_config *cfg)
+{
+ cfg->pwrmbase_offset = PWRMBASE;
+ cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS;
+ cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE;
+ cfg->abase_offset = ABASE;
+ cfg->abase_addr = ACPI_BASE_ADDRESS;
+ cfg->abase_size = ACPI_BASE_SIZE;
+}
static const struct reg_script pch_pmc_misc_init_script[] = {
/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
@@ -58,68 +68,11 @@
REG_SCRIPT_END
};
-static void pch_pmc_add_mmio_resources(device_t dev)
-{
- struct resource *res;
-
- /* Memory-mmapped I/O registers. */
- res = new_resource(dev, PWRMBASE);
- res->base = PCH_PWRM_BASE_ADDRESS;
- res->size = PCH_PWRM_BASE_SIZE;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
- IORESOURCE_FIXED | IORESOURCE_RESERVE;
-}
-
-static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index)
-{
- struct resource *res;
- res = new_resource(dev, index);
- res->base = base;
- res->size = size;
- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void pch_pmc_add_io_resources(device_t dev)
-{
- /* PMBASE */
- pch_pmc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
-}
-
-static void pch_pmc_read_resources(device_t dev)
-{
- /* Get the normal PCI resources of this device. */
- pci_dev_read_resources(dev);
-
- /* Add non-standard MMIO resources. */
- pch_pmc_add_mmio_resources(dev);
-
- /* Add IO resources. */
- pch_pmc_add_io_resources(dev);
-}
-
-static void pch_set_acpi_mode(void)
-{
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
- printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
- outb(APM_CNT_ACPI_DISABLE, APM_CNT);
- printk(BIOS_DEBUG, "done.\n");
- }
-}
-
-static void pch_rtc_init(void)
-{
- /* Ensure the date is set including century byte. */
- cmos_check_update_date();
-
- cmos_init(rtc_failure());
-}
-
static void pch_power_options(void)
{
u16 reg16;
const char *state;
- /*PMC Controller Device 0x1F, Func 02*/
- device_t dev = PCH_DEV_PMC;
+
/* Get the chip configuration */
int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
@@ -133,7 +86,7 @@
/*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/
//get_option(&pwr_on, "power_on_after_fail");
pwr_on = MAINBOARD_POWER_ON;
- reg16 = pci_read_config16(dev, GEN_PMCON_B);
+ reg16 = pci_read_config16(PCH_DEV_PMC, GEN_PMCON_B);
reg16 &= 0xfffe;
switch (pwr_on) {
case MAINBOARD_POWER_OFF:
@@ -151,7 +104,7 @@
default:
state = "undefined";
}
- pci_write_config16(dev, GEN_PMCON_B, reg16);
+ pci_write_config16(PCH_DEV_PMC, GEN_PMCON_B, reg16);
printk(BIOS_INFO, "Set power %s after power failure.\n", state);
/* Set up GPE configuration. */
@@ -199,45 +152,24 @@
write32(pmcbase + DSX_CFG, reg);
}
-static void pmc_init(struct device *dev)
+void pmc_init(struct device *dev)
{
- config_t *config = dev->chip_info;
+ const config_t *config = dev->chip_info;
- pch_rtc_init();
+ rtc_init();
/* Initialize power management */
pch_power_options();
/* Note that certain bits may be cleared from running script as
* certain bit fields are write 1 to clear. */
- reg_script_run_on_dev(dev, pch_pmc_misc_init_script);
- pch_set_acpi_mode();
+ reg_script_run_on_dev(PCH_DEV_PMC, pch_pmc_misc_init_script);
+ pmc_set_acpi_mode();
config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
config_deep_sx(config->deep_sx_config);
/* Clear registers that contain write-1-to-clear bits. */
- reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
+ reg_script_run_on_dev(PCH_DEV_PMC, pmc_write1_to_clear_script);
}
-
-static struct device_operations device_ops = {
- .read_resources = &pch_pmc_read_resources,
- .set_resources = &pci_dev_set_resources,
- .enable_resources = &pci_dev_enable_resources,
- .init = &pmc_init,
- .scan_bus = &scan_lpc_bus,
- .ops_pci = &soc_pci_ops,
-};
-
-static const unsigned short pci_device_ids[] = {
- 0x9d21,
- 0xa121,
- 0
-};
-
-static const struct pci_driver pch_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = pci_device_ids,
-};
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 6dbe718..8bfbfea 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,5 +1,4 @@
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += car_stage.S
-romstage-y += pmc.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/pmc.c b/src/soc/intel/skylake/romstage/pmc.c
deleted file mode 100644
index e9d06f2..0000000
--- a/src/soc/intel/skylake/romstage/pmc.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-
-void pmc_set_disb(void)
-{
- /* Set the DISB after DRAM init */
- u32 disb_val = 0;
- pci_devfn_t dev = PCH_DEV_PMC;
- disb_val = pci_read_config32(dev, GEN_PMCON_A);
- disb_val |= DISB;
-
- /* Don't clear bits that are write-1-to-clear */
- disb_val &= ~(GBL_RST_STS | MS4V);
- pci_write_config32(dev, GEN_PMCON_A, disb_val);
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I042bf62407b0acee3d24fbba2de2d482c3fbff9a
Gerrit-Change-Number: 22565
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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