[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Add Intel common PMC controller support
Subrata Banik (Code Review)
gerrit at coreboot.org
Wed Nov 22 14:34:50 CET 2017
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22563
Change subject: soc/intel/common/block: Add Intel common PMC controller support
......................................................................
soc/intel/common/block: Add Intel common PMC controller support
SoC need to select specific macros to compile commom
PMC code.
Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
A src/soc/intel/common/block/include/intelblocks/pmc.h
M src/soc/intel/common/block/pmc/Makefile.inc
A src/soc/intel/common/block/pmc/pmc.c
3 files changed, 178 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/22563/1
diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h
new file mode 100644
index 0000000..f693b51
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/pmc.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_PMC_H
+#define SOC_INTEL_COMMON_BLOCK_PMC_H
+
+#include <device/device.h>
+#include <stdint.h>
+
+/*
+ * SoC overrides
+ *
+ * All new SoC must implement below functionality.
+ */
+
+/* Function to initialize PMC controller.
+ *
+ * This initialization may differ between different SoC
+ *
+ * Input: Device Structure PMC PCI device
+ */
+void pmc_init(struct device *dev);
+
+/* PMC controller resource structure */
+struct pmc_resource_config {
+ uint8_t pwrmbase_offset;
+ uintptr_t pwrmbase_addr;
+ size_t pwrmbase_size;
+ uint8_t abase_offset;
+ uintptr_t abase_addr;
+ size_t abase_size;
+};
+
+/*
+ * SoC should fill this structure information based on
+ * PMC controller register information like PWRMBASE, ABASE offset
+ * BAR and Size
+ */
+void soc_pch_pmc_get_resources(struct pmc_resource_config *cfg);
+
+/* API to set ACPI mode */
+void pmc_set_acpi_mode(void);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */
diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc
index 40fcba1..2253115 100644
--- a/src/soc/intel/common/block/pmc/Makefile.inc
+++ b/src/soc/intel/common/block/pmc/Makefile.inc
@@ -1,5 +1,8 @@
-bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
-smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
-verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmclib.c
+ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC),y)
+bootblock-y += pmclib.c
+romstage-y += pmclib.c
+ramstage-y += pmc.c
+ramstage-y += pmclib.c
+smm-y += pmclib.c
+verstage-y += pmclib.c
+endif
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
new file mode 100644
index 0000000..a4b2960
--- /dev/null
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/pmc.h>
+#include <soc/pci_devs.h>
+
+/* SoC overrides */
+
+/* Fill up PMC resource structure inside SoC directory */
+__attribute__((weak)) void soc_pch_pmc_get_resources(
+ struct pmc_resource_config *cfg)
+{
+ /* no-op */
+}
+
+/* SoC override PMC initialization */
+__attribute__((weak)) void pmc_init(struct device *dev)
+{
+ /* no-op */
+}
+
+static void pch_pmc_add_mmio_resources(device_t dev, uint8_t offset,
+ uintptr_t pwrm_base, size_t pwrm_size)
+{
+ struct resource *res;
+
+ /* Memory-mapped I/O registers. */
+ res = new_resource(dev, offset);
+ res->base = pwrm_base;
+ res->size = pwrm_size;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+ IORESOURCE_FIXED | IORESOURCE_RESERVE;
+}
+
+static void pch_pmc_add_io_resources(device_t dev, uint8_t offset,
+ uintptr_t abase, size_t size)
+{
+ struct resource *res;
+
+ res = new_resource(dev, offset);
+ res->base = abase;
+ res->size = size;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void pch_pmc_read_resources(device_t dev)
+{
+ static struct pmc_resource_config *config;
+
+ soc_pch_pmc_get_resources(config);
+
+ if (!config->pwrmbase_offset)
+ die("Unable to get PMC controller resource information!");
+
+ /* Get the normal PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add non-standard MMIO resources. */
+ pch_pmc_add_mmio_resources(dev, config->pwrmbase_offset,
+ config->pwrmbase_addr, config->pwrmbase_size);
+
+ /* Add IO resources. */
+ pch_pmc_add_io_resources(dev, config->abase_offset,
+ config->abase_addr, config->abase_size);
+}
+
+void pmc_set_acpi_mode(void)
+{
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
+ printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+ outb(APM_CNT_ACPI_DISABLE, APM_CNT);
+ printk(BIOS_DEBUG, "done.\n");
+ }
+}
+
+static struct device_operations device_ops = {
+ .read_resources = &pch_pmc_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .init = &pmc_init,
+ .scan_bus = &scan_lpc_bus,
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_SPT_LP_PMC,
+ PCI_DEVICE_ID_INTEL_KBP_H_PMC,
+ PCI_DEVICE_ID_INTEL_APL_PMC,
+ PCI_DEVICE_ID_INTEL_GLK_PMC,
+ PCI_DEVICE_ID_INTEL_CNL_PMC,
+ 0
+};
+
+static const struct pci_driver pch_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e
Gerrit-Change-Number: 22563
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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