[coreboot-gerrit] Change in coreboot[master]: mainboard/google/kahlee: Add Baseboard GPIOs
Martin Roth (Code Review)
gerrit at coreboot.org
Tue Nov 21 00:21:19 CET 2017
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22546
Change subject: mainboard/google/kahlee: Add Baseboard GPIOs
......................................................................
mainboard/google/kahlee: Add Baseboard GPIOs
Add initial baseboard GPIOs based on grunt schematics.
BUG=b:69305596
TEST=Build grunt
Change-Id: I4efcee7dbf54fb9ea82e5e9394db805bb69203c8
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/mainboard/google/kahlee/variants/baseboard/gpio.c
M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl
M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
3 files changed, 324 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/22546/1
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
index 4dc6d45..f07f538 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -21,6 +21,228 @@
static const GPIO_CONTROL agesa_board_gpios[] = {
+ /* GPIO_0 - EC_PCH_PWR_BTN_ODL */
+ { 0, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_1 - SYS_RST_ODL */
+ { 1, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */
+ { 2, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_3 - Unused (R145) */
+ { 3, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_4 - EN_PP3300_WLAN */
+ { 4, Function0, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */
+ { 5, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */
+ { 6, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_7 - APU_PWROK_OD */
+ { 7, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_8 - DDR_ALERT_3V3_L, SCI */
+ { 8, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_9 - PCH_INT_ODL, SCI */
+ { 9, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_10 - SLP_S0_L */
+ { 10, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_11 - Unused (R166) */
+ { 11, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_12 - Unused (TP126) */
+ { 12, Function2, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_13 - APU_PEN_PDCT_ODL, SCI */
+ { 13, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_14 - APU_HP_INT_ODL, SCI */
+ { 14, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_15 - EC_IN_RW_OD */
+ { 15, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_16 - USB_C0_OC_L, SCI */
+ { 16, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_17 - USB_C1_OC_L, SCI */
+ { 17, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_18 - USB_A0_OC_ODL, SCI */
+ { 18, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_19 - APU_I2C_SCL3 (Touchscreen) */
+ { 19, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_20 - APU_I2C_SDA3 (Touchscreen) */
+ { 20, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_21 - Unused (TP23) */
+ { 21, Function1, FCH_GPIO_PULL_DOWN_ENABLE },
+
+ /* GPIO_22 - EC_SCI_ODL */
+ { 22, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_23 - ACOK_OD */
+ /* GPIO_24 - USB_A1_OC_ODL, SCI */
+ { 24, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_25 - SD_CD */
+ { 25, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_26 - APU_PCIE_RST_L */
+ { 26, Function0, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_40 - TOUCHSCREEN_INT_3V3_ODL, SCI */
+ { 40, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_42 - S5_MUX_CTRL */
+ { 42, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE },
+
+ /* GPIO_67 - PEN_RESET */
+ { 67, Function0, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_70 - WLAN_PE_RST */
+ { 70, Function0, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_74 - LPC_CLK0_EC_R */
+ { 74, Function0, FCH_GPIO_PULL_DOWN_ENABLE },
+
+ /* GPIO_75 - LPC_CLK1 */
+ { 75, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_76 - EN_PP3300_TOUCHSCREEN */
+ { 76, Function0, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_84 - HUB_RST */
+ { 84, Function1, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_85 - TOUCHSCREEN_RST_1V8 */
+ { 85, Function1, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_86 - Unused (TP109) */
+ { 86, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_87 - LPC_SERIRQ */
+ { 87, Function0, },
+
+ /* GPIO_88 - LPC_CLKRUN_L */
+ { 88, Function0, },
+
+ /* GPIO_90 - EN_PP3300_CAMERA */
+ { 90, Function0, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_91 - EN_PP3300_TRACKPAD */
+ { 91, Function1, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */
+ { 92, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_93 - Unused (TP129) */
+ { 93, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_95 - SD_CLK */
+ /* GPIO_96 - SD_CMD */
+ /* GPIO_97 - SD_D0 */
+ /* GPIO_98 - SD_D1 */
+ /* GPIO_99 - SD_D2 */
+ /* GPIO_100 - SD_D3 */
+
+ /* GPIO_101 - SD_WP_L */
+ { 101, Function0, FCH_GPIO_PULL_DOWN_ENABLE },
+
+ /* GPIO_102 - EN_SD_SOCKET_PWR */
+ { 102, Function0, FCH_GPIO_PULL_DOWN_ENABLE },
+
+ /* GPIO_113 - APU_I2C_SCL2 (Pen & Trackpad) */
+ { 113, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_114 - APU_I2C_SDA2 (Pen & Trackpad) */
+ { 114, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_115 - Unused (TP127) */
+ { 115, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_116 - PCIE_EMMC_CLKREQ_L */
+ { 116, Function0, },
+
+ /* GPIO_117 - PCH_SPI_CLK_R */
+
+ /* GPIO_118 - PCH_SPI_CS0_L */
+ { 118, Function0, },
+
+ /* GPIO_119 - SPK_PA_EN */
+ { 119, Function2, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_120 - PCH_SPI_MISO */
+ /* GPIO_121 - PCH_SPI_MOSI */
+
+ /* GPIO_122 - APU_BIOS_FLASH_WP */
+ { 122, Function1, },
+
+
+ /* GPIO_126 - DMIC_CLK2_EN */
+ { 126, Function1, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_129 - APU_KBRST_L */
+ { 129, Function0, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_130 - APU_PEN_INT_ODL, SCI */
+ { 130, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_131 - CONFIG_STRAP3 */
+ { 131, Function3, },
+
+ /* GPIO_132 - CONFIG_STRAP4 */
+ { 132, Function2, },
+
+ /* GPIO_133 - APU_EDP_BKLTEN (backlight enable) */
+ { 133, Function1, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_135 - Unused (TP128) */
+ { 135, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+ /* GPIO_136 - UART_PCH_RX_DEBUG_TX */
+ { 136, Function0, },
+
+ /* GPIO_137 - AUDIO_CLK_EN */
+ { 137, Function1, FCH_GPIO_OUTPUT_VALUE },
+
+ /* GPIO_138 - UART_PCH_TX_DEBUG_RX */
+ { 138, Function0, },
+
+ /* GPIO_139 - CONFIG_STRAP1 */
+ { 139, Function1, },
+
+ /* GPIO_140 - I2S_BCLK_R */
+ /* GPIO_141 - I2S2_DATA_MIC2 */
+
+ /* GPIO_142 - CONFIG_STRAP2 */
+ { 142, Function1, },
+
+ /* GPIO_143 - I2S2_DATA */
+ /* GPIO_144 - I2S_LR_R */
+
+ /* GPIO_145 - PCH_I2C_AUDIO_SCL */
+ { 145, Function0, },
+
+ /* GPIO_146 - PCH_I2C_AUDIO_SDA */
+ { 146, Function0, },
+
+ /* GPIO_147 - PCH_I2C_HUB_SCL */
+ { 147, Function0, },
+
+ /* GPIO_148 - PCH_I2C_HUB_SDA */
+ { 148, Function0, },
+
+ {-1}
};
const __attribute__((weak)) GPIO_CONTROL *get_gpio_table(void)
@@ -34,6 +256,81 @@
*/
static const struct sci_source gpe_table[] = {
+ /* PCH_TRACKPAD_INT_3V3_ODL */
+ {
+ .scimap = 7,
+ .gpe = 7,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_EDG,
+ },
+
+ /* DDR_ALERT_3V3_L */
+ {
+ .scimap = 23,
+ .gpe = 23,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* PCH_INT_ODL */
+ {
+ .scimap = 22,
+ .gpe = 22,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* APU_PEN_PDCT_ODL */
+ {
+ .scimap = 21,
+ .gpe = 21,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* APU_HP_INT_ODL */
+ {
+ .scimap = 6,
+ .gpe = 6,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* USB_C0_OC_L */
+ {
+ .scimap = 12,
+ .gpe = 12,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* USB_C1_OC_L */
+ {
+ .scimap = 13,
+ .gpe = 13,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* USB_A0_OC_ODL */
+ {
+ .scimap = 14,
+ .gpe = 14,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* USB_A1_OC_ODL */
+ {
+ .scimap = 15,
+ .gpe = 15,
+ .direction = SMI_SCI_LVL_LOW,
+ .level = SMI_SCI_LVL,
+ },
+
+ /* TODO: These pins may need to be moved - No associated GEVENT */
+ /* TOUCHSCREEN_INT_3V3_ODL */
+ /* APU_PEN_INT_ODL */
};
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl
index 72f26d8..a3f5306 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl
@@ -14,16 +14,24 @@
* GNU General Public License for more details.
*/
-/* USB overcurrent mapping pins. */
-Name (UOM0, 0)
-Name (UOM1, 0)
-Name (UOM2, 0)
-Name (UOM3, 0)
-Name (UOM4, 0)
-Name (UOM5, 0)
-Name (UOM6, 0)
-Name (UOM7, 0)
-Name (UOM8, 0)
-Name (UOM9, 0)
+#define NO_OC_PIN 0 /* Gevent 0 is not available on FT4 */
+#define USB_OC_0_GPE 12
+#define USB_OC_1_GPE 13
+#define USB_OC_2_GPE 14
+#define USB_OC_3_GPE 15
+
+/* USB overcurrent mapping pins for 8 EHCI ports. */
+Name (UOM0, NO_OC_PIN) /* Camera - no OC pin */
+Name (UOM1, NO_OC_PIN) /* BT - no OC pin */
+Name (UOM2, NO_OC_PIN) /* Camera2 - no OC pin */
+Name (UOM3, NO_OC_PIN) /* Unused - no OC pin */
+Name (UOM4, USB_OC_0_GPE) /* USB-C 0 */
+Name (UOM5, USB_OC_1_GPE) /* USB-C 1 */
+Name (UOM6, NO_OC_PIN) /* HUB - connect OC pins to HUB */
+Name (UOM7, NO_OC_PIN) /* Unused - no OC pin */
+
+/* The 2 USB-A connectors come off the HUB */
+Name (UOH0, USB_OC_2_GPE) /* USB-A 0 */
+Name (UOH1, USB_OC_3_GPE) /* USB-A 1 */
/* USB Overcurrent GPEs */
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
index 5aca3e8..c003673 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
@@ -19,19 +19,19 @@
#ifndef __ACPI__
#include <soc/gpio.h>
-# define MEM_CONFIG0 GPIO_0
-# define MEM_CONFIG1 GPIO_0
-# define MEM_CONFIG2 GPIO_0
-# define MEM_CONFIG3 GPIO_0
+# define MEM_CONFIG0 GPIO_139
+# define MEM_CONFIG1 GPIO_142
+# define MEM_CONFIG2 GPIO_131
+# define MEM_CONFIG3 GPIO_132
/* SPI Write protect */
-#define CROS_WP_GPIO GPIO_0
-#define GPIO_EC_IN_RW GPIO_0
+#define CROS_WP_GPIO GPIO_122
+#define GPIO_EC_IN_RW GPIO_15
#endif /* _ACPI__ */
-#define EC_SCI_GPI 0
+#define EC_SCI_GPI 22
-#define EC_SMI_GPI 0
+#define EC_SMI_GPI 6
#endif /* __BASEBOARD_GPIO_H__ */
--
To view, visit https://review.coreboot.org/22546
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4efcee7dbf54fb9ea82e5e9394db805bb69203c8
Gerrit-Change-Number: 22546
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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