[coreboot-gerrit] Change in coreboot[master]: Create soc.asl
Richard Spiegel (Code Review)
gerrit at coreboot.org
Mon Nov 20 20:30:49 CET 2017
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22541
Change subject: Create soc.asl
......................................................................
Create soc.asl
Request from commit 519680948b466d786c618286ac1e8baa9cc6e22c, merge
several includes into a single file in soc directory.
To match comment, rename soc_fch.asl to southbridge.asl. Then copy
the required section from dsdt.asl into a new soc.asl.
Affected boards: amd/gardenia and google/kahlee.
BUG=b:69368752
Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/mainboard/amd/gardenia/dsdt.asl
M src/mainboard/google/kahlee/dsdt.asl
A src/soc/amd/stoneyridge/acpi/soc.asl
R src/soc/amd/stoneyridge/acpi/southbridge.asl
4 files changed, 34 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/22541/1
diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl
index bc81602..2800fe7 100644
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -61,19 +61,8 @@
Name(_STA, 0x0B)
}
- Device(PCI0) {
- /* Describe the AMD Northbridge */
- #include <northbridge.asl>
-
- /* Describe the AMD Fusion Controller Hub Southbridge */
- #include <fch.asl>
- }
-
- /* Describe PCI INT[A-H] for the Southbridge */
- #include <pci_int.asl>
-
- /* Describe the devices in the Southbridge */
- #include <soc_fch.asl>
+ /* describe the soc */
+ #include <soc.asl>
} /* End \_SB scope */
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index 885dd8d..fa0f520 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -61,19 +61,8 @@
Name(_UID, 0xAA)
}
- Device(PCI0) {
- /* Describe the AMD Northbridge */
- #include <northbridge.asl>
-
- /* Describe the AMD Fusion Controller Hub Southbridge */
- #include <fch.asl>
- }
-
- /* Describe PCI INT[A-H] for the Southbridge */
- #include <pci_int.asl>
-
- /* Describe the devices in the Southbridge */
- #include <soc_fch.asl>
+ /* describe the soc */
+ #include <soc.asl>
} /* End \_SB scope */
diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl
new file mode 100644
index 0000000..96ae31d
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/soc.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(PCI0) {
+ /* Describe the AMD Northbridge */
+ #include <northbridge.asl>
+
+ /* Describe the AMD Fusion Controller Hub Southbridge */
+ #include <fch.asl>
+}
+
+/* Describe PCI INT[A-H] for the Southbridge */
+#include <pci_int.asl>
+
+/* Describe the devices in the Southbridge */
+#include <southbridge.asl>
diff --git a/src/soc/amd/stoneyridge/acpi/soc_fch.asl b/src/soc/amd/stoneyridge/acpi/southbridge.asl
similarity index 100%
rename from src/soc/amd/stoneyridge/acpi/soc_fch.asl
rename to src/soc/amd/stoneyridge/acpi/southbridge.asl
--
To view, visit https://review.coreboot.org/22541
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce
Gerrit-Change-Number: 22541
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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