[coreboot-gerrit] Change in coreboot[master]: intel/sandybridge: Don't hardcode platform type
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Mon Nov 20 10:33:35 CET 2017
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/22530
Change subject: intel/sandybridge: Don't hardcode platform type
......................................................................
intel/sandybridge: Don't hardcode platform type
* Add a function to return CPU platform ID bits
* Add a function to return platform type
* Use introduced method to handle platform specific code
Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
M src/cpu/intel/model_206ax/Makefile.inc
A src/cpu/intel/model_206ax/common.c
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/model_206ax/model_206ax_init.c
M src/mainboard/intel/cougar_canyon2/romstage.c
M src/northbridge/intel/fsp_sandybridge/Makefile.inc
M src/northbridge/intel/fsp_sandybridge/early_init.c
M src/northbridge/intel/fsp_sandybridge/northbridge.h
M src/northbridge/intel/sandybridge/Makefile.inc
A src/northbridge/intel/sandybridge/common.c
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/report_platform.c
M src/northbridge/intel/sandybridge/romstage.c
M src/northbridge/intel/sandybridge/sandybridge.h
M src/southbridge/intel/fsp_i89xx/romstage.c
18 files changed, 123 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/22530/1
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
index 7516e9d..1628e2d 100644
--- a/src/cpu/intel/model_206ax/Makefile.inc
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -5,6 +5,10 @@
ramstage-y += acpi.c
+ramstage-y += common.c
+romstage-y += common.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c
+
ramstage-y += tsc_freq.c
romstage-y += tsc_freq.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c
new file mode 100644
index 0000000..23691a2
--- /dev/null
+++ b/src/cpu/intel/model_206ax/common.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <cpu/x86/msr.h>
+#include "model_206ax.h"
+
+#define IA32_PLATFORM_ID 0x17
+
+int get_platform_id(void)
+{
+ msr_t msr;
+
+ /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
+ msr = rdmsr(IA32_PLATFORM_ID);
+ return (msr.hi >> 18) & 0x7;
+}
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 594dde1..d5bbac8 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -101,5 +101,6 @@
int cpu_config_tdp_levels(void);
void smm_relocate(void);
#endif
+int get_platform_id(void);
#endif
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index ed5c292..1385fd6 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -514,6 +514,9 @@
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Print platform ID */
+ printk(BIOS_INFO, "CPU: PlatID %x\n", get_platform_id());
+
/* Setup MTRRs based on physical address size */
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 96c22ea..ff53e0e 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -196,7 +196,7 @@
sandybridge_sb_early_initialization();
post_code(0x43);
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ sandybridge_early_initialization();
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
post_code(0x44);
diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
index 2a4d9bd..76c3f0c 100644
--- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc
+++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
@@ -23,6 +23,10 @@
ramstage-y += acpi.c
+ramstage-y += common.c
+romstage-y += common.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c
+
romstage-y += raminit.c
romstage-y += ram_calc.c
romstage-y += early_init.c
diff --git a/src/northbridge/intel/fsp_sandybridge/early_init.c b/src/northbridge/intel/fsp_sandybridge/early_init.c
index 1afb6cd..30ae649 100644
--- a/src/northbridge/intel/fsp_sandybridge/early_init.c
+++ b/src/northbridge/intel/fsp_sandybridge/early_init.c
@@ -60,7 +60,7 @@
#endif
}
-void sandybridge_early_initialization(int chipset_type)
+void sandybridge_early_initialization(void)
{
u32 capid0_a;
u8 reg8;
@@ -68,10 +68,12 @@
/* Device ID Override Enable should be done very early */
capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
if (capid0_a & (1 << 10)) {
+ const enum platform_type type = get_platform_type();
+
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
reg8 &= ~7; /* Clear 2:0 */
- if (chipset_type == SANDYBRIDGE_MOBILE)
+ if (type == platform_mobile)
reg8 |= 1; /* Set bit 0 */
pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index c0194f2..aa698de 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -18,11 +18,6 @@
#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
-/* Chipset types */
-#define SANDYBRIDGE_MOBILE 0
-#define SANDYBRIDGE_DESKTOP 1
-#define SANDYBRIDGE_SERVER 2
-
/* Device ID for SandyBridge and IvyBridge */
#define BASE_REV_SNB 0x00
#define BASE_REV_IVB 0x50
@@ -63,6 +58,14 @@
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* Chipset types */
+enum platform_type {
+ platform_mobile = 0,
+ platform_desktop,
+ platform_server
+};
/* Device 0:0.0 PCI configuration space (Host Bridge) */
@@ -203,7 +206,7 @@
void intel_sandybridge_finalize_smm(void);
#else /* !__SMM__ */
int bridge_silicon_revision(void);
-void sandybridge_early_initialization(int chipset_type);
+void sandybridge_early_initialization(void);
void sandybridge_late_initialization(void);
/* debugging functions */
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 846d31b..3cfc53e 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -24,6 +24,11 @@
ramstage-y += acpi.c
romstage-y += ram_calc.c
+
+ramstage-y += common.c
+romstage-y += common.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c
+
ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
romstage-y += raminit.c
romstage-y += raminit_common.c
diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c
new file mode 100644
index 0000000..b5a3544
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/common.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "sandybridge.h"
+
+enum platform_type get_platform_type(void)
+{
+ const int id = get_platform_id();
+ switch (id)
+ {
+ case 1:
+ return platform_desktop;
+ case 4:
+ return platform_mobile;
+ case 7:
+ return platform_server;
+ default:
+ printk(BIOS_ERR, "Unknown platform id 0x%x\n", id);
+ return platform_mobile;
+ }
+}
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 2f1b790..fd0b5ca 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -186,7 +186,7 @@
}
}
-void sandybridge_early_initialization(int chipset_type)
+void sandybridge_early_initialization(void)
{
u32 capid0_a;
u32 deven;
@@ -195,10 +195,12 @@
/* Device ID Override Enable should be done very early */
capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
if (capid0_a & (1 << 10)) {
+ const enum platform_type type = get_platform_type();
+
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
reg8 &= ~7; /* Clear 2:0 */
- if (chipset_type == SANDYBRIDGE_MOBILE)
+ if (type == platform_mobile)
reg8 |= 1; /* Set bit 0 */
pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 12384b4..c0cb9a4 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -304,7 +304,7 @@
return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size);
}
-static void init_dram_ddr3(int mobile, int min_tck, int s3resume)
+static void init_dram_ddr3(int min_tck, int s3resume)
{
int me_uma_size;
int cbmem_was_inited;
@@ -393,7 +393,6 @@
if (!fast_boot) {
/* Reset internal state */
memset(&ctrl, 0, sizeof(ctrl));
- ctrl.mobile = mobile;
ctrl.tCK = min_tck;
/* Get architecture */
@@ -416,7 +415,6 @@
/* Reset internal state */
memset(&ctrl, 0, sizeof(ctrl));
- ctrl.mobile = mobile;
ctrl.tCK = min_tck;
/* Get architecture */
@@ -475,5 +473,5 @@
timestamp_add_now(TS_BEFORE_INITRAM);
- init_dram_ddr3(1, get_mem_min_tck(), s3resume);
+ init_dram_ddr3(get_mem_min_tck(), s3resume);
}
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index eaef5f7..f08fc38 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -760,6 +760,7 @@
{
u16 mr0reg, mch_cas, mch_wr;
static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 };
+ const size_t is_mobile = get_platform_type() == platform_mobile;
/* DLL Reset - self clearing - set after CLK frequency has been changed */
mr0reg = 0x100;
@@ -780,7 +781,7 @@
mr0reg = (mr0reg & ~0xe00) | (mch_wr << 9);
// Precharge PD - Fast (desktop) 0x1 or slow (mobile) 0x0 - mostly power-saving feature
- mr0reg = (mr0reg & ~0x1000) | (!ctrl->mobile << 12);
+ mr0reg = (mr0reg & ~0x1000) | (!is_mobile << 12);
return mr0reg;
}
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index ab6e592..6ce2453 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -75,7 +75,6 @@
typedef struct ramctr_timing_st {
u16 spd_crc[NUM_CHANNELS][NUM_SLOTS];
- int mobile;
int sandybridge;
/* DDR base_freq = 100 Mhz / 133 Mhz */
diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c
index d137e8b..575bd3c 100644
--- a/src/northbridge/intel/sandybridge/report_platform.c
+++ b/src/northbridge/intel/sandybridge/report_platform.c
@@ -48,6 +48,7 @@
cpuidr = cpuid(1);
printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_name);
+ printk(BIOS_DEBUG, "CPU platform ID: %x\n", get_platform_id());
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 8608d5a..a5ec37e 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -86,7 +86,7 @@
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ sandybridge_early_initialization();
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
s3resume = southbridge_detect_s3_resume();
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index dd1a58c..41fef22 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -17,11 +17,6 @@
#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
-/* Chipset types */
-#define SANDYBRIDGE_MOBILE 0
-#define SANDYBRIDGE_DESKTOP 1
-#define SANDYBRIDGE_SERVER 2
-
/* Device ID for SandyBridge and IvyBridge */
#define BASE_REV_SNB 0x00
#define BASE_REV_IVB 0x50
@@ -61,6 +56,14 @@
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* Chipset types */
+enum platform_type {
+ platform_mobile = 0,
+ platform_desktop,
+ platform_server
+};
#include <rules.h>
@@ -205,7 +208,7 @@
void intel_sandybridge_finalize_smm(void);
#else /* !__SMM__ */
int bridge_silicon_revision(void);
-void sandybridge_early_initialization(int chipset_type);
+void sandybridge_early_initialization(void);
void sandybridge_init_iommu(void);
void sandybridge_late_initialization(void);
void northbridge_romstage_finalize(int s3resume);
@@ -226,6 +229,7 @@
void mainboard_config_superio(void);
int mainboard_should_reset_usb(int s3resume);
void perform_raminit(int s3resume);
+enum platform_type get_platform_type(void);
#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index a089720..1b6e595 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -119,7 +119,7 @@
sandybridge_sb_early_initialization();
post_code(0x43);
- sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ sandybridge_early_initialization();
printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
post_code(0x44);
--
To view, visit https://review.coreboot.org/22530
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ifbfc64c8cec98782d6efc987a4d4d5aeab1402ba
Gerrit-Change-Number: 22530
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro at das-labor.org>
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