[coreboot-gerrit] Change in coreboot[master]: mainboard/google/fizz: Enable separate MRC cache for recovery mode

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/22518


Change subject: mainboard/google/fizz: Enable separate MRC cache for recovery mode
......................................................................

mainboard/google/fizz: Enable separate MRC cache for recovery mode

Enable separate MRC cache for recovery mode. This requires change in
flash layout to accomodate another region for RECOVERY_MRC_CACHE.

BUG=b:69473883
TEST=Verified following scenarios:
1. Boot into recovery does not destroy normal mode MRC cache.
2. Once recovery MRC cache is populated, all future boots in recovery
mode re-use data from the cache.
3. Forcing recovery mode to retrain memory causes normal mode to retrain
memory as well.

Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648
Signed-off-by: Shelley Chen <shchen at chromium.org>
---
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/fizz/chromeos.fmd
2 files changed, 20 insertions(+), 13 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/22518/1

diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 6474824..b1f353d 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -26,6 +26,8 @@
 	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
 	select VBOOT_EC_EFS
 	select VBOOT_PHYSICAL_REC_SWITCH
+	select HAS_RECOVERY_MRC_CACHE
+	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 
 config DRIVER_TPM_I2C_BUS
 	depends on FIZZ_USE_I2C_TPM
diff --git a/src/mainboard/google/fizz/chromeos.fmd b/src/mainboard/google/fizz/chromeos.fmd
index 58b6127..bdadcf7 100644
--- a/src/mainboard/google/fizz/chromeos.fmd
+++ b/src/mainboard/google/fizz/chromeos.fmd
@@ -4,24 +4,29 @@
 		SI_ME at 0x1000 0x1ff000
 	}
 	SI_BIOS at 0x200000 0xe00000 {
-		RW_SECTION_A at 0x0 0x3f0000 {
+		RW_SECTION_A at 0x0 0x3e8000 {
 			VBLOCK_A at 0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x3dffc0
-			RW_FWID_A at 0x3effc0 0x40
+			FW_MAIN_A(CBFS)@0x10000 0x3d7fc0
+			RW_FWID_A at 0x3e7fc0 0x40
 		}
-		RW_SECTION_B at 0x3f0000 0x3f0000 {
+		RW_SECTION_B at 0x3e8000 0x3e8000 {
 			VBLOCK_B at 0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x3dffc0
-			RW_FWID_B at 0x3effc0 0x40
+			FW_MAIN_B(CBFS)@0x10000 0x3d7fc0
+			RW_FWID_B at 0x3e7fc0 0x40
 		}
-		RW_MRC_CACHE at 0x7e0000 0x10000
-		RW_ELOG at 0x7f0000 0x4000
-		RW_SHARED at 0x7f4000 0x4000 {
-			SHARED_DATA at 0x0 0x2000
-			VBLOCK_DEV at 0x2000 0x2000
+		RW_MISC at 0x7d0000 0x30000 {
+			UNIFIED_MRC_CACHE at 0x0 0x20000 {
+				RECOVERY_MRC_CACHE at 0x0 0x10000
+				RW_MRC_CACHE at 0x10000 0x10000
+			}
+			RW_ELOG at 0x20000 0x4000
+			RW_SHARED at 0x24000 0x4000 {
+				SHARED_DATA at 0x0 0x2000
+				VBLOCK_DEV at 0x2000 0x2000
+			}
+			RW_VPD at 0x28000 0x2000
+			RW_NVRAM at 0x2a000 0x6000
 		}
-		RW_VPD at 0x7f8000 0x2000
-		RW_NVRAM at 0x7fa000 0x6000
 		RW_LEGACY(CBFS)@0x800000 0x200000
 		WP_RO at 0xa00000 0x400000 {
 			RO_VPD at 0x0 0x4000

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648
Gerrit-Change-Number: 22518
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen at google.com>
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