[coreboot-gerrit] Change in coreboot[master]: google/fizz: correct memory rcomp settings

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/22479


Change subject: google/fizz: correct memory rcomp settings
......................................................................

google/fizz: correct memory rcomp settings

Follow the schematic and Doc 573387 to correct the rcomp and
rcomp target settings for fizz

Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Signed-off-by: Kane Chen <kane.chen at intel.com>
---
M src/mainboard/google/fizz/romstage.c
1 file changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22479/1

diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c
index 405c4c1..335662e 100644
--- a/src/mainboard/google/fizz/romstage.c
+++ b/src/mainboard/google/fizz/romstage.c
@@ -24,9 +24,9 @@
 	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
 	const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
 	/* Rcomp resistor */
-	const u16 rcomp_resistor[] = { 200, 81, 162 };
+	const u16 rcomp_resistor[] = { 121, 81, 100 };
 	/* Rcomp target */
-	const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
+	const u16 rcomp_target[] = { 100, 40, 20, 20, 26 };
 
 	/* SPD was saved in S0/S5 path, skips it when resumes from S3 */
 	if (arch_upd->BootMode == FSP_BOOT_ON_S3_RESUME)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Gerrit-Change-Number: 22479
Gerrit-PatchSet: 1
Gerrit-Owner: Kane Chen <kane.chen at intel.com>
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