[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge/include/amd_pci_int_types.h fix
Richard Spiegel (Code Review)
gerrit at coreboot.org
Wed Nov 15 20:18:10 CET 2017
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22476
Change subject: amd/stoneyridge/include/amd_pci_int_types.h fix
......................................................................
amd/stoneyridge/include/amd_pci_int_types.h fix
Strings table intr_types is based on Hudson. Stoneyridge APIC is organized
differently, some strings represent APIC registers that don't exist in
Stoneyridge, while some of Stoneyridge APIC registers are not represented
in the table.Fix the table, paying attention to the correct index for each
valid register.
amd_pci_int_defs.h must be fixed to reflect the new amd_pci_int_types.h.
BUG=b:62200834
Change-Id: I18907c93e1eec341d56cea13bb73a336d8e7b05b
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/common/include/amd/common/amd_pci_int_defs.h
M src/soc/amd/stoneyridge/include/amd_pci_int_types.h
2 files changed, 10 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22476/1
diff --git a/src/soc/amd/common/include/amd/common/amd_pci_int_defs.h b/src/soc/amd/common/include/amd/common/amd_pci_int_defs.h
index a8e75f63..4fafd6c 100644
--- a/src/soc/amd/common/include/amd/common/amd_pci_int_defs.h
+++ b/src/soc/amd/common/include/amd/common/amd_pci_int_defs.h
@@ -44,23 +44,17 @@
#define PIRQ_ASF 0x12 /* ASF */
#define PIRQ_HDA 0x13 /* HDA 14h.2 */
#define PIRQ_FC 0x14 /* FC */
-#define PIRQ_GEC 0x15 /* GEC */
#define PIRQ_PMON 0x16 /* Performance Monitor */
#define PIRQ_SD 0x17 /* SD */
+#define PIRQ_SDIO 0x1a /* SDIO */
#define PIRQ_IMC0 0x20 /* IMC INT0 */
#define PIRQ_IMC1 0x21 /* IMC INT1 */
#define PIRQ_IMC2 0x22 /* IMC INT2 */
#define PIRQ_IMC3 0x23 /* IMC INT3 */
#define PIRQ_IMC4 0x24 /* IMC INT4 */
#define PIRQ_IMC5 0x25 /* IMC INT5 */
-#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */
-#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */
-#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */
-#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */
-#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */
-#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */
-#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */
-#define PIRQ_IDE 0x40 /* IDE 14h.1 */
+#define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */
+#define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */
#define PIRQ_SATA 0x41 /* SATA 11h.0 */
#define FCH_INT_TABLE_SIZE 0x76
diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
index 08bdc10..39e0fe3 100644
--- a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
@@ -21,17 +21,17 @@
"INTF#\t", "INTG#\t", "INTH#\t",
[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA",
"Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
- [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t",
- "PerMon\t", "SD\t\t",
+ [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t",
+ [0x16] = "PerMon\t", "SD\t\t",
+ [0x1a] = "SDIO\t",
[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t",
"IMC INT4\t", "IMC INT5\t",
- [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB",
- "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
- [0x7f] = "RSVD\t",
- [0x40] = "IDE\t", "SATA\t",
- [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
+ [0x30] = "EHCI\t",
+ [0x34] = "XHCI\t",
+ [0x41] = "SATA\t",
[0x62] = "GPIO\t",
[0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t",
+ [0x7f] = "RSVD\t",
};
#endif /* __AMD_PCI_INT_TYPES_H__ */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I18907c93e1eec341d56cea13bb73a336d8e7b05b
Gerrit-Change-Number: 22476
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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