[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add 50ns delay before EMMC D0
Lijian Zhao (Code Review)
gerrit at coreboot.org
Tue Nov 14 23:21:54 CET 2017
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22390
Change subject: soc/intel/cannonlake: Add 50ns delay before EMMC D0
......................................................................
soc/intel/cannonlake: Add 50ns delay before EMMC D0
Add 50ns delay for EMMC before bring up from D3 to D0.
TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform.
Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/cannonlake/acpi/scs.asl
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/22390/5
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
index 11564ae..d85bff8 100644
--- a/src/soc/intel/cannonlake/acpi/scs.asl
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -14,6 +14,17 @@
*/
Scope (\_SB.PCI0) {
+ /* EMMC */
+ Device(PEMC) {
+ Name(_ADR, 0x001A0000)
+
+ Method(_PS0, 0, Serialized) {
+ Stall (50) // Sleep 50us
+ }
+
+ Method(_PS3, 0, Serialized) {
+ }
+ }
/* SD CARD */
Device (SDXC)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Gerrit-Change-Number: 22390
Gerrit-PatchSet: 5
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: AndreX Andraos <andrex.andraos at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar at intel.com>
Gerrit-Reviewer: Wei-nan Liu <wei-nan.liu at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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