[coreboot-gerrit] Change in coreboot[master]: mb/google/eve: Tune I2C4 hold times

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/22448


Change subject: mb/google/eve: Tune I2C4 hold times
......................................................................

mb/google/eve: Tune I2C4 hold times

Tune PCH I2C4 hold times to ensure the frequency is always <400KHz.

BUG=b:67029862
TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz

Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950
Original-Signed-off-by: Duncan Laurie <dlaurie at google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/739841
Original-Reviewed-by: Furquan Shaikh <furquan at chromium.org>
---
M src/mainboard/google/eve/devicetree.cb
1 file changed, 6 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22448/1

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 3b87fd1..50926da 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -198,8 +198,12 @@
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
 	register "i2c[4]" = "{
 		.speed = I2C_SPEED_FAST,
-		.rise_time_ns = 240,
-		.fall_time_ns = 30,
+		.speed_config[0] = {
+			.speed = I2C_SPEED_FAST,
+			.scl_lcnt = 176,
+			.scl_hcnt = 95,
+			.sda_hold = 36,
+		}
 	}"
 
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1
Gerrit-Change-Number: 22448
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
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