[coreboot-gerrit] Change in coreboot[master]: mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5

[Ben Chan (Code Review)]

Ben Chan has uploaded this change for review. ( https://review.coreboot.org/22415


Change subject: mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5
......................................................................

mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5

On Astronaunt, after the system enters the S5 power state, there is a
10-second timeout before the system transitions the power state from S5
to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78
on the APL platform, remains on during that period. If the system is
powered back on before going to G3, the built-in modem won't go through
a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted.

Keeping the modem, and indirectly the SIM, powered during a quick system
power cycle may sometimes be undesirable. For instance, we would like a
SIM with PIN lock enabled to require unlocking each time the system is
powered on. After the SIM receives a PIN, it may remain unlocked until
its next power cycle.

Also, it is often desirable to power cycle the modem when the system
goes through a power cycle. For instance, a user may power cycle the
system to recover a wedged modem.

BUG=b:68365029
TEST=Tested the following on an Astronaunt device:
1. Verify that the modem is powered on after the system boots from cold.
2. Suspend the system to S0ix. Verify that the modem remains powered on
   when the system is in S0ix. After the system goes back to S0, verify
   that the SIM with PIN lock enabled doesn't request unlocking, and the
   modem can quickly reconnect to a network.
3. Configure the system to suspend to S3 instead of S0ix, and then
   repeat (2).
4. Perform a quick system power cycle, verify that the modem is powered
   cycle and the SIM with PIN lock enabled requests unlocking.

Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2
Signed-off-by: Ben Chan <benchan at chromium.org>
---
M src/mainboard/google/reef/smihandler.c
M src/mainboard/google/reef/variants/baseboard/gpio.c
M src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/reef/variants/coral/gpio.c
4 files changed, 21 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/22415/1

diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index d8b4702..6bc5190 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -35,7 +35,7 @@
 	const struct pad_config *pads;
 	size_t num;
 
-	pads = variant_sleep_gpio_table(&num);
+	pads = variant_sleep_gpio_table(slp_typ, &num);
 	gpio_configure_pads(pads, num);
 
 	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c
index 5aa9f77..7440cf8 100644
--- a/src/mainboard/google/reef/variants/baseboard/gpio.c
+++ b/src/mainboard/google/reef/variants/baseboard/gpio.c
@@ -376,7 +376,7 @@
 };
 
 const struct pad_config * __attribute__((weak))
-variant_sleep_gpio_table(size_t *num)
+variant_sleep_gpio_table(u8 slp_typ, size_t *num)
 {
 	*num = ARRAY_SIZE(sleep_gpio_table);
 	return sleep_gpio_table;
diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h
index 18fbf54..3e30ccb 100644
--- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h
@@ -28,7 +28,7 @@
  * entries for each table. */
 const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
-const struct pad_config *variant_sleep_gpio_table(size_t *num);
+const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num);
 
 /* Baseboard default swizzle. Can be reused if swizzle is same. */
 extern const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle;
diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c
index 8e9f04c..e89e5b5 100644
--- a/src/mainboard/google/reef/variants/coral/gpio.c
+++ b/src/mainboard/google/reef/variants/coral/gpio.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/acpi.h>
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
@@ -368,16 +369,28 @@
 	return early_gpio_table;
 }
 
-/* GPIO settings before entering sleep. */
-static const struct pad_config sleep_gpio_table[] = {
+/* Default GPIO settings before entering sleep. */
+static const struct pad_config default_sleep_gpio_table[] = {
 	PAD_CFG_GPO(GPIO_150, 0, DEEP),		/* NFC_RESET_ODL */
 	PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP),	/* NFC_INT_L */
 };
 
-const struct pad_config *variant_sleep_gpio_table(size_t *num)
+/* GPIO settings before entering S5, which are same as default_sleep_gpio_table
+ * but also turn off EN_PP3300_DX_LTE_SOC. */
+static const struct pad_config s5_sleep_gpio_table[] = {
+	PAD_CFG_GPO(GPIO_150, 0, DEEP),		/* NFC_RESET_ODL */
+	PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP),	/* NFC_INT_L */
+	PAD_CFG_GPO(GPIO_78, 0, DEEP),		/* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
+};
+
+const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
 {
-	*num = ARRAY_SIZE(sleep_gpio_table);
-	return sleep_gpio_table;
+	if (slp_typ == ACPI_S5) {
+		*num = ARRAY_SIZE(s5_sleep_gpio_table);
+		return s5_sleep_gpio_table;
+	}
+	*num = ARRAY_SIZE(default_sleep_gpio_table);
+	return default_sleep_gpio_table;
 }
 
 static const struct cros_gpio cros_gpios[] = {

-- 
To view, visit https://review.coreboot.org/22415
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2
Gerrit-Change-Number: 22415
Gerrit-PatchSet: 1
Gerrit-Owner: Ben Chan <benchan at chromium.org>
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