[coreboot-gerrit] Change in coreboot[master]: kahlee: Add thermal ASL

Marc Jones (Code Review) gerrit at coreboot.org
Thu Nov 9 21:00:03 CET 2017


Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22400


Change subject: kahlee: Add thermal ASL
......................................................................

kahlee: Add thermal ASL

Connect the EC thermal to Kahlee thermal ASL. Intialize GNVS
thermal values in the mainboard finalize.

BUG=b:67999819

Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3
Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
A src/mainboard/google/kahlee/acpi/thermal.asl
M src/mainboard/google/kahlee/dsdt.asl
M src/mainboard/google/kahlee/mainboard.c
A src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h
4 files changed, 156 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/22400/1

diff --git a/src/mainboard/google/kahlee/acpi/thermal.asl b/src/mainboard/google/kahlee/acpi/thermal.asl
new file mode 100644
index 0000000..3d53364
--- /dev/null
+++ b/src/mainboard/google/kahlee/acpi/thermal.asl
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/thermal.h>
+
+/* Thermal Zone */
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		/* Thermal constants for passive cooling */
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		/* Thermal zone polling frequency: 10 seconds */
+		Name (_TZP, 100)
+
+		/* Thermal sampling period for passive cooling: 2 seconds */
+		Name (_TSP, 20)
+
+		/* Convert from Degrees C to 1/10 Kelvin for ACPI */
+		Method (CTOK, 1) {
+			/* 10th of Degrees C */
+			Multiply (Arg0, 10, Local0)
+
+			/* Convert to Kelvin */
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		/* Threshold for OS to shutdown */
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		/* Threshold for passive cooling */
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		/* Processors used for passive cooling */
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			/* Get temperature from EC in deci-kelvin */
+			Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0)
+
+			/* Critical temperature in deci-kelvin */
+			Store (CTOK (\TCRT), Local1)
+
+			If (LGreaterEqual (Local0, Local1)) {
+				Store ("CRITICAL TEMPERATURE", Debug)
+				Store (Local0, Debug)
+
+				/* Wait 1 second for EC to re-poll */
+				Sleep (1000)
+
+				/* Re-read temperature from EC */
+				Store (\_SB.PCI0.LPCB.EC0.TSRD (TMPS), Local0)
+
+				Store ("RE-READ TEMPERATURE", Debug)
+				Store (Local0, Debug)
+			}
+
+			Return (Local0)
+		}
+
+		/* No active fan controll (_ACx) on Kahlee */
+	}
+}
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index f3f8aaa..963f7d1 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -77,6 +77,9 @@
 
 	} /* End \_SB scope */
 
+	/* Thermal handler */
+	#include "acpi/thermal.asl"
+
 	/* Chrome OS specific */
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index c7689c8..1532d33 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -18,9 +18,12 @@
 #include <arch/acpi.h>
 #include <agesawrapper.h>
 #include <amd_pci_util.h>
+#include <cbmem.h>
 #include <ec.h>
 #include <mainboard.h>
+#include <soc/nvs.h>
 #include <soc/smi.h>
+#include <variant/thermal.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /***********************************************************
@@ -104,7 +107,24 @@
 	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
+
+static void mainboard_final(void *chip_info)
+{
+	struct global_nvs_t *gnvs;
+
+	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+
+	if (gnvs) {
+		gnvs->tmps = CTL_TDP_SENSOR_ID;
+		gnvs->tcrt = CRITICAL_TEMPERATURE;
+		gnvs->tpsv = PASSIVE_TEMPERATURE;
+		gnvs->tmax = MAX_TEMPERATURE;
+		gnvs->flvl = 1;
+	}
+}
+
 struct chip_operations mainboard_ops = {
 	.init = mainboard_init,
 	.enable_dev = kahlee_enable,
+	.final = mainboard_final,
 };
diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h
new file mode 100644
index 0000000..a511215
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/include/variant/thermal.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/*
+ * Stoney Ridge Thermal Requirements 12 (6W)
+ * TDP (W) 6
+ * T die,max (°C) 95
+ * T ctl,max 85
+ * T die,lmt (default) 90
+ * T ctl,lmt (default) 80
+ */
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID		0	/* EC TIN0 */
+#define CTL_TDP_THRESHOLD_OFF		85	/* Normal at 85C */
+#define CTL_TDP_THRESHOLD_ON		90	/* Limited at 90C */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE		94
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE		85
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE			95
+
+#endif

-- 
To view, visit https://review.coreboot.org/22400
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3
Gerrit-Change-Number: 22400
Gerrit-PatchSet: 1
Gerrit-Owner: Marc Jones <marc at marcjonesconsulting.com>
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